公开(公告)号：US20190229019A1

公开(公告)日：2019-07-25

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US20190131428A1

公开(公告)日：2019-05-02

申请号：US15797723

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Jinsheng Gao

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, the sacrificial gate structure comprising a sacrificial gate insulation layer and a multi-layer sacrificial gate electrode structure, removing the sacrificial gate structure to form a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

公开(公告)号：US10224330B2

公开(公告)日：2019-03-05

申请号：US15407960

申请日：2017-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L27/00 ,  H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned junction structures and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for first type devices; and a plurality epitaxial grown fin structures for second type devices having sidewall liners.

公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US10002827B2

公开(公告)日：2018-06-19

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  G03F1/36 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20180061969A1

公开(公告)日：2018-03-01

申请号：US15793419

申请日：2017-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/22 ,  H01L21/311 ,  H01L21/285 ,  H01L21/225 ,  H01L29/207

CPC classification number: H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L23/48 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L2223/00

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US20180033870A1

公开(公告)日：2018-02-01

申请号：US15219370

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Xintuo Dai

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

公开(公告)号：US09812365B1

公开(公告)日：2017-11-07

申请号：US15286117

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Haigou Huang ,  Xusheng Wu ,  Ruilong Xie ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31056 ,  H01L21/31144 ,  H01L29/66545 ,  H01L29/66636

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

公开(公告)号：US09607989B2

公开(公告)日：2017-03-28

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Yue Hu ,  Xin Wang ,  Yong Meng Lee ,  Wen-Pin Peng ,  Lun Zhao ,  Wei-Hua Tong

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

公开(公告)号：US09508794B2

公开(公告)日：2016-11-29

申请号：US15002000

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Xiang Hu ,  Wanxun He

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/161 ,  H01L29/201 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/201

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract translation: 非平面半导体结构包括混合的n型和p型凸起半导体结构，例如具有在其顶表面上生长的外延结构的散热片，例如外延硅和硅锗，天然生长成菱形。 外延结构的表面积通过去除其部分而增加，当另一种类型生长然后随后通过去除而修饰时，掩蔽每种类型。 移除可以与类似于Y形的相应凸起结构的颈部一起产生多头（例如，双头）外延结构。