公开(公告)号：US10700173B2

公开(公告)日：2020-06-30

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20200152736A1

公开(公告)日：2020-05-14

申请号：US16188408

申请日：2018-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong Yu ,  Hui Zang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768 ,  H01L21/033

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

公开(公告)号：US10580685B2

公开(公告)日：2020-03-03

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Hong Yu ,  Laertis Economikos

IPC: H01L23/522 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/764

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

公开(公告)号：US10522679B2

公开(公告)日：2019-12-31

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar Jha ,  Hong Yu ,  Xinyuan Dou ,  Xusheng Wu ,  Dongil Choi ,  Edmund K. Banghart ,  Md Khaled Hassan

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US10475890B2

公开(公告)日：2019-11-12

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hui Zang ,  Hong Yu ,  Zhenyu Hu ,  Scott Beasor ,  Erik Geiss ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20190035633A1

公开(公告)日：2019-01-31

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US10090382B1

公开(公告)日：2018-10-02

申请号：US15811957

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xinyuan Dou ,  Hui Zhan ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/027

Abstract: The disclosure relates to forming single diffusion break (SDB) and end isolation regions in an integrated circuit (IC) structure, and resulting structures. An IC structure according to the disclosure includes: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of gate structures; at least one single diffusion break (SDB) region positioned within the insulator region and one of the plurality of fins, the at least one SDB extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of gate structures.

公开(公告)号：US10043713B1

公开(公告)日：2018-08-07

申请号：US15591814

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu ,  Xing Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US10014296B1

公开(公告)日：2018-07-03

申请号：US15487636

申请日：2017-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xinyuan Dou ,  Hong Yu ,  Sipeng Gu ,  Yanzhen Wang

IPC: H01L21/761 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.

公开(公告)号：US09478622B2

公开(公告)日：2016-10-25

申请号：US14849335

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

Abstract translation: 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。