公开(公告)号：US09825031B1

公开(公告)日：2017-11-21

申请号：US15229292

申请日：2016-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Jason E. Stephens ,  David M. Permana ,  Jagannathan Vasudevan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L27/0886 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795

Abstract: A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a liner layer. A first conductive feature is formed in the first contact opening and a second conductive feature is formed in the second contact opening. A portion of the liner layer adjacent a top surface of the first dielectric layer is removed to define a recess. A barrier layer is formed above the first dielectric layer and in the recess. The barrier layer has a first dielectric constant greater than a second dielectric constant of the first dielectric layer. A second dielectric layer is formed above the barrier layer. A third conductive feature is formed embedded in the second dielectric layer and contacting the second conductive feature.

公开(公告)号：US20150279999A1

公开(公告)日：2015-10-01

申请号：US14732938

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

Abstract translation: 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少一部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US09117908B2

公开(公告)日：2015-08-25

申请号：US14107279

申请日：2013-12-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7856 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

Abstract translation: 所公开的一种方法包括：在牺牲材料层的堆叠中形成牺牲栅极结构沟槽，在沟槽内形成牺牲栅极结构，执行至少一个处理操作以移除堆叠的牺牲材料层的至少部分，从而暴露侧壁 形成邻近牺牲栅极结构的暴露的侧壁的侧壁间隔物，去除牺牲栅极结构，以在间隔物之间​​限定替换栅极腔，在置换栅腔中形成替代栅极结构，并形成 位于置换门腔内的替换栅极结构上方的栅极盖。

公开(公告)号：US09117842B2

公开(公告)日：2015-08-25

申请号：US13798429

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Shao Ming Koh

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66606 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming at least one fin for a FinFET device in a semiconducting substrate, performing at least one process operation to form a region in the at least one fin that contains a metal diffusion inhibiting material, depositing a layer of metal on the region in the at least one fin and forming a metal silicide region on the at least one fin.

Abstract translation: 在一个示例中，本文公开的方法包括在半导体衬底中形成用于FinFET器件的至少一个鳍，执行至少一个工艺操作以在至少一个鳍中形成包含金属扩散抑制材料的区域， 的至少一个翅片上的区域上的金属，并在所述至少一个翅片上形成金属硅化物区域。

公开(公告)号：US20150214059A1

公开(公告)日：2015-07-30

申请号：US14166660

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

公开(公告)号：US20150123214A1

公开(公告)日：2015-05-07

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US20160268171A1

公开(公告)日：2016-09-15

申请号：US14644269

申请日：2015-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 翅片间隔件形成在至少一个翅片的至少第一部分上。 翅片间隔件具有上表面。 所述至少一个翅片是凹入的，从而限定具有凹陷的上表面的凹陷翅片，所述凹陷的翅片在所述翅片间隔件的上表面下方。 第一外延材料形成在凹形鳍上。 第一外延材料的横向延伸受到翅片间隔件约束。 在第一外延材料上形成盖层。 拆下翅片垫片。 盖层在去除鳍片间隔件期间保护第一外延材料。

公开(公告)号：US20160172493A1

公开(公告)日：2016-06-16

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L27/092 ,  H01L29/08 ,  H01L29/24 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：在PFET区域和NFET区域中提供具有鳍状结构的鳍状结构的源极/漏极区域。 该方法包括在PFET区域中的源/漏区上选择性地形成接触电阻调制材料。 此外，该方法包括沉积覆盖PFET区域和NFET区域中的源极/漏极区域的带边功函数金属。

公开(公告)号：US20160141206A1

公开(公告)日：2016-05-19

申请号：US14543992

申请日：2014-11-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.

Abstract translation: 一种方法包括形成具有嵌入其中的至少一个导电特征的第一电介质层。 形成嵌入在设置在第一电介质层上方的第二电介质层中的第一多个导电线。 多个导线中的第一导线接触导电特征。 使用第一蚀刻掩模蚀刻第一导电线以在第一导电线中限定导电通路部分和凹陷线部分。 形成嵌入在第二电介质层上方的第三电介质层中的第二多个导电线。 第二多个导电线中的第二导线接触导电通路部分，第三电介质层直接接触第二电介质层。

公开(公告)号：US20160093713A1

公开(公告)日：2016-03-31

申请号：US14963378

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

Abstract translation: 晶体管器件包括半导体衬底和位于半导体衬底表面之上的栅极结构。 栅极结构包括位于半导体衬底的表面上方的高k栅极绝缘层和位于高k栅极绝缘层上方的材料的至少一个功函数调节层，其中该至少一个工件的上表面 当在晶体管器件的栅极宽度方向上截取的横截面中观察时，材料的功能调节层具有阶梯形轮廓。 栅极结构还包括位于至少一个功函数调节层材料的阶梯状上表面上的导电材料层。