公开(公告)号：US20170287829A1

公开(公告)日：2017-10-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US20170250111A1

公开(公告)日：2017-08-31

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US20170053966A1

公开(公告)日：2017-02-23

申请号：US14832108

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chung H. Lam ,  Chung-Hsun Lin ,  Darsen D. Lu ,  Philip J. Oldiges

IPC: H01L27/24 ,  H01L29/08 ,  H01L45/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/2436 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L45/06

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

Abstract translation: 实施例涉及一种形成鳍型场效应晶体管（FinFET）器件的部分的方法。 该方法包括形成具有多个侧面的至少一个源极区域，形成至少一个具有多个边的漏极区域，形成具有多个边的至少一个沟道区域，在该至少一个沟道区域的多个边缘周围形成至少一个栅极区域 以及在所述至少一个漏极区域的所述多个侧面周围形成所述至少一个栅极区域。

公开(公告)号：US09385026B2

公开(公告)日：2016-07-05

申请号：US14272691

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate.

Abstract translation: 一方面，用于形成开尔文可测试结构的基于DSA的方法包括以下步骤。 引导图案形成在衬底上，其限定i）开尔文可测试结构的多个焊盘区域，以及ii）将衬底上的两个衬垫区域互连的区域。 自组装材料沉积在衬底上，并在足以使其经历自组装以在衬底上形成自组装图案的温度/持续时间退火，其中自组装由引导图案引导 互连两个焊盘区域的区域中的自组装材料形成多个直线。 自组装材料的图案被转移到在衬底中形成多条线的衬底，其中自组装材料的图案被配置为使得只有给定的一条线是两个焊盘区域之间的连续线 底物。

公开(公告)号：US09825094B2

公开(公告)日：2017-11-21

申请号：US14953702

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chung H. Lam ,  Chung-Hsun Lin ,  Darsen D. Lu ,  Philip J. Oldiges

IPC: H01L29/66 ,  H01L27/24 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L45/00 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L27/2436 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L45/06

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

公开(公告)号：US09680020B2

公开(公告)日：2017-06-13

申请号：US14794997

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

公开(公告)号：US09530860B2

公开(公告)日：2016-12-27

申请号：US14578768

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Pranita Kerber ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1083 ,  H01L29/205 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.

Abstract translation: 提供了通过使用卤素掺杂的底部（III-V）阻挡层来控制III-V MOSFET中的短沟道效应的技术。 在一个方面，提供了一种形成MOSFET器件的方法。 该方法包括以下步骤：在衬底上形成III-V阻挡层; 在与衬底相对的III-V阻挡层的一侧上形成III-V沟道层，其中III-V势垒层被配置为将MOSFET器件中的电荷载流子限制到III-V沟道层; 在与III-V阻挡层相对的III-V沟道层的一侧上形成栅叠层; 以及在栅堆叠的相对侧上的III-V阻挡层中形成晕轮植入物。 还提供MOSFET器件。

公开(公告)号：US09281397B2

公开(公告)日：2016-03-08

申请号：US14158539

申请日：2014-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey Sleight

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7845

Abstract: A semiconductor device (e.g., field effect transistor (FET)) having an asymmetric feature, includes a first gate formed on a substrate, first and second diffusion regions formed in the substrate on a side of the first gate, and first and second contacts which contact the first and second diffusion regions, respectively, the first contact being asymmetric with respect to the second contact.

Abstract translation: 具有不对称特征的半导体器件（例如，场效应晶体管（FET））包括形成在衬底上的第一栅极，形成在第一栅极一侧的衬底中的第一和第二扩散区域以及第一和第二触点， 分别与第一和第二扩散区接触，第一触点相对于第二触点是不对称的。

公开(公告)号：US10014214B2

公开(公告)日：2018-07-03

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US09991167B2

公开(公告)日：2018-06-05

申请号：US15085077

申请日：2016-03-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.