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    SHAPED GATE CAPS IN DIELECTRIC-LINED OPENINGS
    1.
    发明申请
    SHAPED GATE CAPS IN DIELECTRIC-LINED OPENINGS 审中-公开

    公开(公告)号：US20200335594A1

    公开(公告)日：2020-10-22

    申请号：US16386545

    申请日：2019-04-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Shesh Mani Pandey

    IPC: H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L21/321

    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

    Interconnect structures with reduced capacitance
    2.
    发明授权
    Interconnect structures with reduced capacitance 审中-公开

    公开(公告)号：US10672710B2

    公开(公告)日：2020-06-02

    申请号：US16000174

    申请日：2018-06-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

    IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

    Device with diffusion blocking layer in source/drain region
    5.
    发明授权
    Device with diffusion blocking layer in source/drain region 有权

    公开(公告)号：US10164099B2

    公开(公告)日：2018-12-25

    申请号：US15889367

    申请日：2018-02-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

    Abstract: One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.

    Source/drain profile engineering for enhanced p-MOSFET
    10.
    发明授权
    Source/drain profile engineering for enhanced p-MOSFET 有权
    增强型p-MOSFET的源极/漏极配置文件工程

    公开(公告)号：US09419082B2

    公开(公告)日：2016-08-16

    申请号：US14259726

    申请日：2014-04-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Shiv Kumar Mishra ,  Zhiqing Li ,  Scott Beasor ,  Shesh Mani Pandey

    IPC: H01L21/22 ,  H01L29/36 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

    CPC classification number: H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

    Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

    Abstract translation: 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

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