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    Method of forming a semiconductor device structure and such a semiconductor device structure
    4.
    发明授权
    Method of forming a semiconductor device structure and such a semiconductor device structure 有权
    形成半导体器件结构的方法和这种半导体器件结构

    公开(公告)号：US09472642B2

    公开(公告)日：2016-10-18

    申请号：US14693978

    申请日：2015-04-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45

    CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

    Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

    Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

    Efficient main spacer pull back process for advanced VLSI CMOS technologies
    6.
    发明授权
    Efficient main spacer pull back process for advanced VLSI CMOS technologies 有权
    先进的VLSI CMOS技术的高效主间隔回拉工艺

    公开(公告)号：US09343374B1

    公开(公告)日：2016-05-17

    申请号：US14527207

    申请日：2014-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jan Hoentschel ,  Peter Javorka ,  Stefan Flachowsky ,  Ralf Richter

    IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

    CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

    Abstract translation: 形成包括在硅化之前拉回间隔物的多晶硅器件，并提供所得到的器件。 实施例包括在基板的上表面上形成两个多晶硅栅叠层; 在第二多晶硅栅叠层上形成硬掩模; 在所述第一多晶硅栅叠层的相对侧用硅帽形成eSiGe; 移除硬掩模; 在每个多晶硅栅极堆叠的相对侧形成氮化物间隔物; 在第二多晶硅栅叠层的相对侧形成深源极/漏极区; 在每个多晶硅栅极堆叠周围形成厚度小于距离基板的上表面的多晶硅栅叠层高度的厚度的填充层; 将氮化物间隔物的上部分除去湿间隙填充层的高度，然后除去湿间隙填充层; 并执行深源极/漏极区和硅帽的硅化。

    Methods of making integrated circuits and components thereof
    9.
    发明授权
    Methods of making integrated circuits and components thereof 有权
    制造集成电路及其组件的方法

    公开(公告)号：US09257530B1

    公开(公告)日：2016-02-09

    申请号：US14471660

    申请日：2014-08-28

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

    IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283

    CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

    Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。

    Methods of removing gate cap layers in CMOS applications
    10.
    发明授权
    Methods of removing gate cap layers in CMOS applications 有权
    在CMOS应用中去除栅极帽层的方法

    公开(公告)号：US09224655B2

    公开(公告)日：2015-12-29

    申请号：US13792540

    申请日：2013-03-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

    IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

    Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

    Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

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