公开(公告)号：US10529728B2

公开(公告)日：2020-01-07

申请号：US15883975

申请日：2018-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L29/66 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11519 ,  H01L29/423 ,  H01L27/11529 ,  H01L27/11534 ,  H01L29/43

Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

公开(公告)号：US10079242B2

公开(公告)日：2018-09-18

申请号：US15366425

申请日：2016-12-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Thomas Melde ,  Elke Erben

IPC: H01L29/10 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L27/11573 ,  H01L21/033 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L27/1237 ,  H01L29/0649 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7841 ,  H01L29/78654 ,  H01L29/78684 ,  H01L2029/42388

Abstract: Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

公开(公告)号：US20180108668A1

公开(公告)日：2018-04-19

申请号：US15831833

申请日：2017-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Jan Paul

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/12

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1207 ,  H01L29/42328 ,  H01L29/42336

Abstract: An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

公开(公告)号：US20180047738A1

公开(公告)日：2018-02-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/161 ,  H01L27/12 ,  H01L29/788

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

公开(公告)号：US20170125432A1

公开(公告)日：2017-05-04

申请号：US14982228

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/0649 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.

公开(公告)号：US20160315162A1

公开(公告)日：2016-10-27

申请号：US15201838

申请日：2016-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: A semiconductor device structure includes an active region positioned in a semiconductor substrate and a gate structure of a transistor positioned above the active region. The gate structure includes a gate insulating layer, a gate metal layer positioned above the gate insulating layer and a trimmed gate electrode material layer positioned above the gate metal layer. A length of at least a portion of the trimmed gate electrode material layer in a gate length direction of the transistor is less than a length of at least the gate metal layer in the gate length direction.

Abstract translation: 半导体器件结构包括位于半导体衬底中的有源区和位于有源区上方的晶体管的栅极结构。 栅极结构包括栅极绝缘层，位于栅极绝缘层上方的栅极金属层和位于栅极金属层上方的修整的栅电极材料层。 在晶体管的栅极长度方向上的修整的栅电极材料层的至少一部分的长度小于栅极金属层在栅极长度方向上的长度。

公开(公告)号：US20160233318A1

公开(公告)日：2016-08-11

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US09412859B2

公开(公告)日：2016-08-09

申请号：US13792730

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

公开(公告)号：US09373720B2

公开(公告)日：2016-06-21

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09373509B2

公开(公告)日：2016-06-21

申请号：US14477358

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Peter Javorka ,  Jan Hoentschel

IPC: H01L21/30 ,  C23C14/48 ,  H01L21/336 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/26586 ,  H01J37/32412 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract translation: 公开了将掺杂剂注入到具有均匀的掺杂剂和所得器件的浓度和深度水平的鳍式场效应晶体管（FINFET）鳍表面上的方法。 实施例包括用于脉冲掺杂物垂直于衬底的上表面的方法，形成注入束脉冲; 对注入束脉冲施加电场或磁场，以实现注入束脉冲的曲线轨迹路径; 以及通过所述注入束脉冲的曲线轨迹路径将所述掺杂剂注入到所述衬底的上表面上的靶FINFET鳍的侧壁表面上。