WIRING SUBSTRATE
    2.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240341033A1

    公开(公告)日:2024-10-10

    申请号:US18625662

    申请日:2024-04-03

    申请人: IBIDEN CO., LTD.

    IPC分类号: H05K1/11 H05K3/40

    摘要: A wiring substrate includes a first build-up part including first insulating and conductor layers, and via conductors, and a second build-up part including second insulating and conductor layers. The first build-up part is laminated on the second build-up part. The minimum wiring width of wirings in the first conductor layers is smaller than the minimum wiring width of wirings in the second conductor layers. The minimum inter-wiring distance of the wirings in the first conductor layers is smaller than the minimum inter-wiring distance of the wirings in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer. The first layer of each via conductor is covering inner wall surface in a via opening and has a first portion and a second portion. The first portion has a portion formed closer to the center of the via opening than the second portion.

    PRINTED WIRING BOARD
    3.
    发明公开

    公开(公告)号:US20240268038A1

    公开(公告)日:2024-08-08

    申请号:US18434888

    申请日:2024-02-07

    申请人: IBIDEN CO., LTD.

    摘要: A printed wiring board includes a first conductor layer, a resin insulating layer including glass particles and resin, a second conductor layer formed on a surface of the resin insulating layer and including a seed layer and an electrolytic plating layer, and a via conductor connecting the first conductor layer and second conductor layer and including the seed layer and electrolytic plating layer extending from the second conductor layer. The second conductor layer and the via conductor are formed such that the second conductor layer includes signal wirings and that the seed layer is formed by sputtering an alloy including copper, aluminum, and one or more metals selected from nickel, zinc, gallium, silicon, and magnesium, and the resin insulating layer is formed such that the surface of the resin insulating layer includes the resin and that an inner wall surface in the opening includes the resin and the glass particles.

    WIRING SUBSTRATE
    5.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240339393A1

    公开(公告)日:2024-10-10

    申请号:US18626395

    申请日:2024-04-04

    申请人: IBIDEN CO., LTD.

    摘要: A wiring substrate includes a first build-up part including first insulating and conductor layers, and via conductors, and a second build-up part including second insulating and conductor layers. The minimum wiring width in the first conductor layers is smaller than the minimum wiring width in the second conductor layers. The minimum inter-wiring distance in the first conductor layers is smaller than the minimum inter-wiring distance in the second conductor layers. Each first conductor layer and each via conductor include first and second layers. The first layer includes a first portion covering respective surface of the first insulating layers, a second portion covering inner wall surface in respective via opening in the first insulating layers, and a third portion covering bottom surface in the respective via opening. The thickness of the first portion is larger than the thickness of the second portion and larger than the thickness of the third portion.

    PRINTED WIRING BOARD
    6.
    发明公开

    公开(公告)号:US20240268021A1

    公开(公告)日:2024-08-08

    申请号:US18434910

    申请日:2024-02-07

    申请人: IBIDEN CO., LTD.

    摘要: A printed wiring board includes a first conductor layer, a resin insulating layer including inorganic particles and resin, a second conductor layer including a seed layer and an electrolytic plating layer, and a via conductor connecting the first conductor layer and second conductor layer and including the seed layer and electrolytic plating layer extending from the second conductor layer. The inorganic particles include first particles, second particles, third particles and fourth particles formed such that the first and second particles are solid particles, the third and fourth particles are hollow particles, the first and third particles form an inner wall surface of the opening in the resin insulating layer, the second and fourth particles are embedded in the resin insulating layer, the first particles have shapes that are different from shapes of the second particles, and the third particles have shapes that are different from shapes of the fourth particles.

    WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:US20240179853A1

    公开(公告)日:2024-05-30

    申请号:US18519524

    申请日:2023-11-27

    申请人: IBIDEN CO., LTD.

    摘要: A wiring substrate includes an insulating layer including inorganic particles and resin, a seed layer formed on a surface of the insulating layer, and a conductor layer including a conductor pattern and formed on the seed layer. The surface of the insulating layer is a roughened surface formed such that the roughened surface of the insulating layer has exposed portions of the inorganic particles and resin with gaps at interfaces where the inorganic particles and the resin are in contact, and the seed layer is formed on the roughened surface of the insulating layer such that the seed layer is formed along the exposed portions of the inorganic particles and resin exposed on the roughened surface of the insulating layer and is not formed in the gaps at the interfaces where the inorganic particles and the resin are in contact.

    PRINTED WIRING BOARD
    8.
    发明公开

    公开(公告)号:US20230328882A1

    公开(公告)日:2023-10-12

    申请号:US18191033

    申请日:2023-03-28

    申请人: IBIDEN CO., LTD.

    发明人: Susumu KAGOHASHI

    IPC分类号: H05K1/11 H05K3/42 H05K1/02

    摘要: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer, and a via conductor formed in an opening formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The via conductor is formed such that the via conductor includes a seed layer covering an inner wall surface of the resin insulating layer inside of the opening and an electrolytic plating layer formed on the seed layer such that the seed layer has a plurality of columnar parts grown in columnar shapes.

    PRINTED WIRING BOARD
    9.
    发明申请

    公开(公告)号:US20230080335A1

    公开(公告)日:2023-03-16

    申请号:US17823210

    申请日:2022-08-30

    申请人: IBIDEN CO., LTD.

    IPC分类号: H05K1/03 H05K3/46 G06T7/00

    摘要: A printed wiring board includes a resin insulating layer including resin and particles, and a conductor layer formed on a surface of the resin insulating layer. The particles in the resin insulating layer include first particles and second particles such that the first particles are partially embedded in the resin and the second particles are completely embedded in the resin, and the resin insulating layer is formed such that the first particles has exposed surfaces exposed from the resin and covered surfaces covered by the resin, respectively, the surface of the resin insulating layer includes the first exposed surfaces, and a ratio of a second area to a first area is in a range of 0.1 to 0.25 where the first area is an area of the surface of the resin insulating layer, and the second area is obtained by summing areas of the exposed surfaces of the first particles.

    WIRING SUBSTRATE
    10.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240363541A1

    公开(公告)日:2024-10-31

    申请号:US18646819

    申请日:2024-04-26

    申请人: IBIDEN CO., LTD.

    IPC分类号: H01L23/538 H01L21/48

    CPC分类号: H01L23/5383 H01L21/4857

    摘要: A wiring substrate includes a first build-up part including first insulating layers, first conductor layers, and first via conductors, and a second build-up part including second insulating layers and second conductor layers. The minimum wiring width and minimum inter-wiring distance in the first conductor layers are smaller than the minimum wiring width and minimum inter-wiring distance in the second conductor layers. The first conductor layers and via conductors include a first layer and a second layer formed on the first layer. The first layer includes a lower layer including a sputtering film including an alloy including copper, aluminum, and at least one element selected from nickel, zinc, gallium, silicon, and magnesium, and an upper layer including a sputtering film including copper. The lower layer is formed in contact with surfaces of the first insulating layers and inner wall surfaces and bottom surfaces in via openings for the first via conductors.