公开(公告)号：US20180323106A1

公开(公告)日：2018-11-08

申请号：US15774446

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANAZ GARDNER ,  SEUNG HOON SUNG

IPC: H01L21/8258 ,  H01L27/06 ,  H01L27/085

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7786

Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.

公开(公告)号：US20200313649A1

公开(公告)日：2020-10-01

申请号：US16882992

申请日：2020-05-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H03H9/17 ,  H03H3/02 ,  H03H9/02 ,  H03H9/13 ,  H03H9/56

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

公开(公告)号：US20200219772A1

公开(公告)日：2020-07-09

申请号：US16239059

申请日：2019-01-03

Applicant: INTEL CORPORATION

Inventor： RAHUL RAMASWAMY ,  NIDHI NIDHI ,  WALID M. HAFEZ ,  JOHANN C. RODE ,  PAUL FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANSAPTAK DASGUPTA

IPC: H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/872 ,  H01L29/66

Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).

公开(公告)号：US20200119030A1

公开(公告)日：2020-04-16

申请号：US16303485

申请日：2016-06-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  PRASHANT MAJHI ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L27/11556 ,  H01L29/08 ,  H01L29/20 ,  H01L29/788 ,  H01L29/36 ,  H01L29/423 ,  H01L29/205 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213

Abstract: Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.

公开(公告)号：US20190229705A1

公开(公告)日：2019-07-25

申请号：US16326590

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  PAUL B. FISCHER ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H03H9/205 ,  H01L27/20 ,  H01L41/187 ,  H01L41/08 ,  H03H3/02 ,  H01L41/316 ,  H01L41/29 ,  H03H9/58 ,  H03H9/60 ,  H03H9/02

Abstract: An integrated circuit film bulk acoustic resonator (FBAR) device having multiple resonator thicknesses is formed on a common substrate in a stacked configuration. In an embodiment, a seed layer is deposited on a substrate, and one or more multi-layer stacks are deposited on the seed layer, each multi-layer stack having a first metal layer deposited on a first sacrificial layer, and a second metal layer deposited on a second sacrificial layer. The second sacrificial layer can be removed and the resulting space is filled in with a piezoelectric material, and the first sacrificial layer can be removed to release the piezoelectric material from the substrate and suspend the piezoelectric material above the substrate. More than one multi-layer stack can be added, each having a unique resonant frequency. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate.

公开(公告)号：US20180331156A1

公开(公告)日：2018-11-15

申请号：US15777511

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L27/20 ,  H03H9/17 ,  H03H9/56 ,  H01L27/06 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H03H3/02 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8258 ,  H01L41/187 ,  H01L41/314 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/20 ,  H01L21/0254 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L41/187 ,  H01L41/314 ,  H03H3/02 ,  H03H9/0542 ,  H03H9/173 ,  H03H9/562 ,  H03H9/564 ,  H03H2003/021

Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate. In a more general sense, the techniques can be used for SoC integration of an RF frontend having diverse III-N componentry on a single substrate, in accordance with some embodiments.

公开(公告)号：US20150171205A1

公开(公告)日：2015-06-18

申请号：US14630541

申请日：2015-02-24

Applicant: Intel Corporation

Inventor： HAN WUI THEN ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract translation: 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：US20190198627A1

公开(公告)日：2019-06-27

申请号：US16326846

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  PAUL B. FISCHER

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/20 ,  H01L29/778 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/735 ,  H01L29/7786

Abstract: Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.

公开(公告)号：US20190189771A1

公开(公告)日：2019-06-20

申请号：US16322816

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  PAUL B. FISCHER

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/762 ,  H01L29/20 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L29/66212 ,  H01L21/76224 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/872

Abstract: Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.

公开(公告)号：US20190088759A1

公开(公告)日：2019-03-21

申请号：US16080824

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.