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公开(公告)号：US20150213900A1
公开(公告)日：2015-07-30
申请号：US14679574
申请日：2015-04-06
Applicant: Intel Corporation
Inventor： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P. Belgal
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.
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公开(公告)号：US09817600B2
公开(公告)日：2017-11-14
申请号：US15377200
申请日：2016-12-13
Applicant: Intel Corporation
Inventor： Ning Wu , Robert E. Frickey , Hanmant P. Belgal , Xin Guo
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0647 , G06F3/065 , G06F3/0688 , G06F11/1417
Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
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公开(公告)号：US20160284399A1
公开(公告)日：2016-09-29
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
Abstract translation: 提供了一种装置，包括：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 提供了一种方法，其包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。
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公开(公告)号：US09384801B2
公开(公告)日：2016-07-05
申请号：US14461154
申请日：2014-08-15
Applicant: INTEL CORPORATION
Inventor： Abhinav Pandey , Hanmant P. Belgal , Prashant S. Damle , Arjun Kripanidhi , Sebastian T. Uribe , Dany-Sebastien Ly-Gagnon , Sanjay Rangan , Kiran Pangal
CPC classification number: G11C7/12 , G06F11/1072 , G11C7/04 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C14/0045 , G11C29/028 , G11C29/50004 , G11C2013/0057 , G11C2029/5004
Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.
Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。
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公开(公告)号：US20170160338A1
公开(公告)日：2017-06-08
申请号：US14961824
申请日：2015-12-07
Applicant: Intel Corporation
Inventor： Christopher F. Connor , Bruce Querbach , Gordon McFadden , Hanmant P. Belgal , Rahul Khanna
CPC classification number: G01R31/2894 , G11C5/04 , G11C7/00 , G11C16/3495 , G11C29/025 , G11C29/16 , G11C29/40 , G11C29/50016 , G11C2029/5004
Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.
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Patent Agency Ranking
公开(公告)号：US09552159B2
公开(公告)日：2017-01-24
申请号：US14877144
申请日：2015-10-07
Applicant: Intel Corporation
Inventor： Ning Wu , Robert E. Frickey , Hanmant P. Belgal , Xin Guo
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0647 , G06F3/065 , G06F3/0688 , G06F11/1417
Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。
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公开(公告)号：US10163502B2
公开(公告)日：2018-12-25
申请号：US15396251
申请日：2016-12-30
Applicant: INTEL CORPORATION
Inventor： Christopher F. Connor , Bruce Querbach , Hanmant P. Belgal
Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.
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公开(公告)号：US09613691B2
公开(公告)日：2017-04-04
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
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公开(公告)号：US20160054925A1
公开(公告)日：2016-02-25
申请号：US14877144
申请日：2015-10-07
Applicant: Intel Corporation
Inventor： Ning Wu , Robert E. Frickey , Hanmant P. Belgal , Xin Guo
IPC: G06F3/06
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0647 , G06F3/065 , G06F3/0688 , G06F11/1417
Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.
Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。
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公开(公告)号：US09490018B2
公开(公告)日：2016-11-08
申请号：US14679574
申请日：2015-04-06
Applicant: Intel Corporation
Inventor： Yogesh B. Wakchaure , Kiran Pangal , Xin Guo , Qingru Meng , Hanmant P. Belgal
IPC: G11C16/16 , G11C16/14 , G11C16/06 , G11C16/04 , G11C16/34 , G11C16/10 , G11C29/02 , G11C16/26 , H01L27/115
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.
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