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公开(公告)号：US20200076046A1
公开(公告)日：2020-03-05
申请号：US16122609
申请日：2018-09-05
Applicant: Intel Corporation
Inventor： Omkar KARHADE , William J. LAMBERT , Xiaoqian LI , Sidharth DALMIA
Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.
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公开(公告)号：US20220256715A1
公开(公告)日：2022-08-11
申请号：US17390601
申请日：2021-07-30
Applicant: Intel Corporation
Inventor： Divya MANI , William J. LAMBERT , Shawna LIFF , Sergio A. CHAN ARGUEDAS , Robert L. SANKMAN
IPC: H05K3/34
Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.
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公开(公告)号：US20220093536A1
公开(公告)日：2022-03-24
申请号：US17030121
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Krishna BHARATH , William J. LAMBERT , Haifa HARIRI , Siddharth KULASEKARAN , Mathew MANUSHAROW , Anne AUGUSTINE
IPC: H01L23/64 , H01L23/00 , H01L23/498 , H01L23/552 , H01L21/48
Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.
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公开(公告)号：US20220093314A1
公开(公告)日：2022-03-24
申请号：US17025537
申请日：2020-09-18
Applicant: Intel Corporation
Inventor： Anuj MODI , Huong DO , William J. LAMBERT , Krishna BHARATH , Harish KRISHNAMURTHY
Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.
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公开(公告)号：US20220094263A1
公开(公告)日：2022-03-24
申请号：US17030132
申请日：2020-09-23
Applicant: Intel Corporation
Inventor： Krishna BHARATH , Christopher SCHAEF , William J. LAMBERT , Kaladhar RADHAKRISHNAN
Abstract: Embodiments disclosed herein include inductor arrays. In an embodiment, an inductor array comprises a first inductor with a first inductance. In an embodiment, the first inductor is switched at a first frequency. In an embodiment, the inductor array further comprises a second inductor with a second inductance that is different than the first inductance. In an embodiment, the second inductor is switched at a second frequency that is different than the first frequency.
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Patent Agency Ranking
公开(公告)号：US20210233867A1
公开(公告)日：2021-07-29
申请号：US16752457
申请日：2020-01-24
Applicant: Intel Corporation
Inventor： Bassam ZIADEH , Joseph VAN NAUSDLE , Zhou YANG , William J. LAMBERT , Mitul MODI
IPC: H01L23/00 , H01L25/065 , H01L23/538 , H01L21/50
Abstract: Embodiments herein describe techniques for an IC package including a supporting layer having a first zone and a second zone. An electronic component is placed above the first zone of the supporting layer. An underfill material is formed above the first zone of the supporting layer, around or below the electronic component to support the electronic component. The second zone of the supporting layer includes a base area and multiple micro-pillars above the base area, where any two micro-pillars of the multiple micro-pillars are separated by a gap in between. The second zone has a hydrophobic surface including surfaces of the multiple micro-pillars and surfaces of the base area. The second zone is a keep out zone to prevent the underfill material from entering the second zone. Other embodiments may be described and/or claimed.
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公开(公告)号：US20200036095A1
公开(公告)日：2020-01-30
申请号：US16465980
申请日：2017-01-04
Applicant: Intel Corporation
Inventor： Adel A. ELSHERBINI , Shawna M. LIFF , William J. LAMBERT
Abstract: Embodiments are generally directed to a package architecture for antenna arrays. An embodiment of an apparatus includes an electronic package, the electronic package including one or more routing layers; a transmitter to drive a signal for wireless transmission; and an assembled phased array antenna to transmit the signal, the assembled phased array antenna including a plurality of separate antenna elements in an array, each antenna element of the array being individually attached to a first side of the electronic package. The antenna elements include a first antenna element and a second antenna element, wherein the first antenna element is separated from the second antenna element by a gap.
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公开(公告)号：US20210125944A1
公开(公告)日：2021-04-29
申请号：US16665682
申请日：2019-10-28
Applicant: Intel Corporation
Inventor： William J. LAMBERT , Sri Chaitra Jyotsna CHAVALI
Abstract: Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.
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公开(公告)号：US20180332708A1
公开(公告)日：2018-11-15
申请号：US15774263
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： William J. LAMBERT , Mihir K. ROY , Mathew J. MANUSHAROW
CPC classification number: H05K1/185 , H01L21/486 , H01L23/49827 , H01L25/16 , H05K1/181 , H05K3/0047 , H05K3/3436 , H05K3/4038 , H05K2201/10015 , H05K2201/1003 , H05K2201/10454 , H05K2201/10515 , H05K2201/10651
Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.
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公开(公告)号：US20180315690A1
公开(公告)日：2018-11-01
申请号：US15773030
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Adel A. ELSHERBINI , Mathew J. MANUSHAROW , Krishna BHARATH , William J. LAMBERT , Robert L. SANKMAN , Aleksandar ALEKSOV , Brandon M. RAWLINGS , Feras EID , Javier SOTO GONZALEZ , Meizi JIAO , Suddhasattwa NAD , Telesphor KAMGAING
CPC classification number: H01F27/40 , H01F17/0006 , H01L28/00
Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
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