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1.发明公开公开(公告)号：US20240113162A1
公开(公告)日：2024-04-04
申请号：US17936417
申请日：2022-09-29
IPC分类号： H01L29/06 , H01L21/8238 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.
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公开(公告)号：US20240006467A1
公开(公告)日：2024-01-04
申请号：US17853293
申请日：2022-06-29
发明人： Julien Frougier , Sagarika Mukesh , Anthony I. Chou , Andrew M. Greene , Ruilong Xie , Nicolas Jean Loubet , Veeraraghavan S. Basker , Junli Wang , Effendi Leobandung , Jingyun Zhang
IPC分类号： H01L49/02 , H01L29/06 , H01L27/06 , H01L29/423 , H01L29/786
CPC分类号： H01L28/24 , H01L29/0665 , H01L27/0629 , H01L29/42392 , H01L29/78696
摘要： A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided. The precision MOL resistor is located over a nanosheet device and is present in at least one resistor device region of a semiconductor substrate. The at least one resistor device region can include a first resistor device region in which the MOL resistor is optimized for low capacitance and/or a second resistor device region in which the MOL resistor is optimized for low self-heating.
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3.发明公开公开(公告)号：US20230335588A1
公开(公告)日：2023-10-19
申请号：US18337074
申请日：2023-06-19
发明人： Takashi Ando , Ruilong Xie , Alexander Reznicek , Jingyun Zhang
IPC分类号： H01L29/06 , H01L21/02 , H01L29/786 , H01L29/66
CPC分类号： H01L29/0665 , H01L21/0259 , H01L29/786 , H01L29/66742 , B82Y40/00
摘要： A method of forming a semiconductor structure includes forming a nanosheet stack on a substrate. The nanosheet stack includes an alternating sequence of sacrificial nanosheets and channel nanosheets. The sacrificial nanosheets include second nanosheets located between first nanosheets and third nanosheets. The first nanosheets and the third nanosheets have a first germanium concentration that is lower than a second germanium concentration of the second nanosheets. The sacrificial nanosheets are selectively etched and the lower first germanium concentration causes the first nanosheets and the third nanosheets to be etched slower than the second nanosheets creating an indentation region on opposing sides of the nanosheet stack. The indentation region has a narrowing shape towards remaining second nanosheets of the sacrificial nanosheets.
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公开(公告)号：US11756960B2
公开(公告)日：2023-09-12
申请号：US17483981
申请日：2021-09-24
发明人： Jingyun Zhang , Takashi Ando , Choonghyun Lee
IPC分类号： H01L27/092 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/28 , H01L21/311 , H01L21/3115 , H01L21/8238 , H01L29/06
CPC分类号： H01L27/0922 , H01L21/02532 , H01L21/02603 , H01L21/28088 , H01L21/28158 , H01L21/3115 , H01L21/31111 , H01L21/31144 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/0673 , H01L29/408 , H01L29/42392 , H01L29/4908 , H01L29/66545 , H01L29/78618 , H01L29/78696 , H01L2029/42388
摘要： A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.
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公开(公告)号：US20230197778A1
公开(公告)日：2023-06-22
申请号：US17557676
申请日：2021-12-21
发明人： Ruilong Xie , Chen Zhang , Jingyun Zhang , PIETRO MONTANINI
IPC分类号： H01L29/06 , H01L29/786 , H01L21/8234
CPC分类号： H01L29/0665 , H01L21/823412 , H01L21/823418 , H01L29/0649 , H01L29/78618 , H01L29/78696
摘要： Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.
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公开(公告)号：US20230187508A1
公开(公告)日：2023-06-15
申请号：US17550724
申请日：2021-12-14
发明人： Ruilong Xie , Jingyun Zhang , Reinaldo Vega , Alexander Reznicek
IPC分类号： H01L29/417 , H01L29/08 , H01L29/40 , H01L29/66
CPC分类号： H01L29/41733 , H01L29/0847 , H01L29/401 , H01L29/66545 , H01L29/42392
摘要： A semiconductor structure includes a source/drain region having a recessed portion. The semiconductor structure further includes a metal contact having a first portion and a second portion. The first portion of the metal contact has a first width and the second portion of the metal contact has a second width greater than the first width. At least a portion of the second portion of the metal contact is disposed in the recessed portion of the source/drain region.
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公开(公告)号：US20230178539A1
公开(公告)日：2023-06-08
申请号：US17545501
申请日：2021-12-08
发明人： Julien Frougier , Sagarika Mukesh , Anthony I. Chou , Andrew M. Greene , Ruilong Xie , Veeraraghavan S. Basker , Junli Wang , Effendi Leobandung , Jingyun Zhang , Nicolas Loubet
IPC分类号： H01L27/02 , H01L27/12 , H01L21/84 , H01L21/8234
CPC分类号： H01L27/0255 , H01L27/1207 , H01L27/0296 , H01L21/84 , H01L27/1211 , H01L21/823481
摘要： A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.
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公开(公告)号：US11527616B2
公开(公告)日：2022-12-13
申请号：US16953447
申请日：2020-11-20
IPC分类号： H01L27/092 , H01L29/78 , H01L29/417 , H01L29/66 , H01L29/10 , H01L29/161 , H01L21/8238 , H01L29/51
摘要： A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed over the first set of fins, and a second high-κ metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.
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9.发明申请公开(公告)号：US20220384574A1
公开(公告)日：2022-12-01
申请号：US17303233
申请日：2021-05-25
发明人： Julien Frougier , Sagarika Mukesh , RUQIANG BAO , Andrew M. Greene , Jingyun Zhang , Nicolas Loubet , Veeraraghavan S. Basker
IPC分类号： H01L29/06 , H01L29/78 , H01L29/423 , H01L29/417
摘要： A semiconductor structure may include one or more nanosheet field-effect transistors formed on a first portion of a substrate, and one or more fin field-effect transistors formed on a second portion of the substrate. A source drain of the one or more nanosheet field-effect transistors or a gate of the one or more nanosheet field-effect transistors may be separated from the substrate by an isolation layer. A source drain of the one or more fin field-effect transistors or a gate of the one or more fin field-effect transistors may be in direct contact with the substrate. The semiconductor structure may include a gate spacer surrounding the gate of the one or more nanosheet field-effect transistors and the gate of the one or more fin field-effect transistors.
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公开(公告)号：US11515214B2
公开(公告)日：2022-11-29
申请号：US17232295
申请日：2021-04-16
发明人： Takashi Ando , Jingyun Zhang , Choonghyun Lee , Pouya Hashemi
IPC分类号： H01L21/8234 , H01L27/088
摘要： Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.
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