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    Chip package with sidewall metallization
    2.
    发明授权
    Chip package with sidewall metallization 有权

    公开(公告)号：US10593615B2

    公开(公告)日：2020-03-17

    申请号：US15970413

    申请日：2018-05-03

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12 ,  H01L23/14

    Abstract: A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.

    ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME 有权
    其制造方法及其制造方法

    公开(公告)号：US20150091183A1

    公开(公告)日：2015-04-02

    申请号：US14042750

    申请日：2013-10-01

    Applicant: Infineon Technologies AG

    Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

    IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

    CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

    Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

    Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

    CHIP PACKAGE WITH SIDEWALL METALLIZATION
    9.
    发明申请
    CHIP PACKAGE WITH SIDEWALL METALLIZATION 审中-公开

    公开(公告)号：US20180323136A1

    公开(公告)日：2018-11-08

    申请号：US15970413

    申请日：2018-05-03

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12

    Abstract: A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices.

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