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公开(公告)号:US20150357736A1
公开(公告)日:2015-12-10
申请号:US14822693
申请日:2015-08-10
Applicant: INTEL CORPORATION
Inventor: Donald T. Tran , Rajasekaran Swaminathan
IPC: H01R12/72 , H01R13/6581 , H01R43/20
CPC classification number: H01R12/721 , H01R12/714 , H01R12/81 , H01R13/6581 , H01R13/6592 , H01R43/205 , Y10T29/49174 , Y10T29/49176
Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
Abstract translation: 本公开的实施例涉及包括边缘指状连接器以及相关联的配置和方法的互连电缆。 边缘指状连接器可以设置在互连电缆的第一端处,并且可以将互连电缆连接到包括在封装衬底中或耦合到封装衬底的边缘指状物。 封装衬底可以包括在处理器封装组件中,并且处理器可以安装在衬底上。 互连电缆可以包括一个或多个细长导体,其中触点直接耦合到相应的导体。 第二连接器可以设置在互连电缆的第二端处,并且可以将互连电缆耦合到被配置为将互连电缆连接到SFP电缆的小型可插拔(SFP)壳体。 可以描述和要求保护其他实施例。
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公开(公告)号:US10541494B2
公开(公告)日:2020-01-21
申请号:US16078613
申请日:2016-03-31
Applicant: Intel Corporation
Inventor: Donald T. Tran , Thomas A. Boyd , Yong Wang , Kevin J. Ceurter , Srikant Nekkanty , Russell S. Aoki , FeiFei Cheng
IPC: H01R13/639 , H01L23/32 , H01R12/71 , H01R13/627 , H01R13/629 , H01R25/00 , H01L23/367
Abstract: Apparatuses, methods and storage medium associated with connectors for coupling to a computer processing unit (CPU) package are disclosed herein. In embodiments, a connector assembly for connection to a computer processing unit (CPU) package may include a connector housing. One or more electrical contacts of the connector housing may be to couple to the CPU package when the connector assembly is engaged with a mating connector assembly. The connector assembly may further include a mounting handle affixed to a top of the connector housing. The mounting handle may include a locking latch that extends from the mounting handle. The locking latch may engage with a notch within the mating connector assembly that, when engaged, the locking latch may provide a force to maintain coupling of the one or more electrical contacts with the CPU package when engaged with the mating connector assembly.
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公开(公告)号:US09118151B2
公开(公告)日:2015-08-25
申请号:US13870938
申请日:2013-04-25
Applicant: Intel Corporation
Inventor: Donald T. Tran , Rajasekaran Swaminathan
IPC: H01R12/00 , H01R12/71 , H01R12/81 , H01R13/6592
CPC classification number: H01R12/721 , H01R12/714 , H01R12/81 , H01R13/6581 , H01R13/6592 , H01R43/205 , Y10T29/49174 , Y10T29/49176
Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
Abstract translation: 本公开的实施例涉及包括边缘指状连接器以及相关联的配置和方法的互连电缆。 边缘指状连接器可以设置在互连电缆的第一端处,并且可以将互连电缆连接到包括在封装衬底中或耦合到封装衬底的边缘指状物。 封装衬底可以包括在处理器封装组件中,并且处理器可以安装在衬底上。 互连电缆可以包括一个或多个细长导体,其中触点直接耦合到相应的导体。 第二连接器可以设置在互连电缆的第二端处,并且可以将互连电缆耦合到被配置为将互连电缆连接到SFP电缆的小型可插拔(SFP)壳体。 可以描述和要求保护其他实施例。
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公开(公告)号:US09076698B2
公开(公告)日:2015-07-07
申请号:US13658380
申请日:2012-10-23
Applicant: INTEL CORPORATION
Inventor: Donald T. Tran , Zhichao Zhang
IPC: H01R12/00 , H05K1/00 , H01L23/13 , H01L23/498
CPC classification number: H01L23/4985 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/17 , H01L24/81 , H01L2224/1601 , H01L2224/16057 , H01L2224/16225 , H01L2224/81801 , H01L2924/0002 , H01L2924/15313 , H01R12/00 , H05K1/00 , Y10T29/49204 , H01L2924/00 , H01L2924/00012
Abstract: A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.
Abstract translation: 一种用于将微电子封装连接到微电子插座的柔性插入器,其中柔性基板的第一部分可以位于微电子封装和微电子插座之间,并且柔性插入件的第二部分可以从微电子封装 以及微电子插座以电接触外部部件。 在一个实施例中,外部组件可以是微电子衬底,并且微电子插座可以附接到微电子衬底。
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公开(公告)号:US20240283197A1
公开(公告)日:2024-08-22
申请号:US18112583
申请日:2023-02-22
Applicant: Intel Corporation
Inventor: Saikat Mondal , Donald T. Tran , Zhichao Zhang , Srikant Nekkanty
IPC: H01R13/6474 , H01R13/6461
CPC classification number: H01R13/6474 , H01R13/6461
Abstract: An apparatus and method for fine tuning impedance in a pin arrangement of a socket are described. The socket has a socket body that contains a plurality of coupling bridges. Each coupling bridge contains: a surrounding portion that at least partially surrounds a via, and a stub portion extending from the ring-shaped portion. Pins inserted in a plurality of vias are arranged in pin pairs configured to support Double Data Rate (DDR) data signals. Each first pin of at least some of the pin pairs electromagnetically coupled to a second pin of these pin pairs using one of the coupling bridges.
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公开(公告)号:US09929511B2
公开(公告)日:2018-03-27
申请号:US15074094
申请日:2016-03-18
Applicant: Intel Corporation
Inventor: John M. Lynch , Chong Richard Zhao , Xiang Li , Donald T. Tran
IPC: H01R12/72 , H01R13/6461 , H01R12/73 , H01R12/75 , H01R13/658 , H01R13/6586 , H01R12/50 , H01R13/6585
CPC classification number: H01R13/6461 , H01R12/72 , H01R12/721 , H01R12/73 , H01R12/737 , H01R12/75 , H01R13/658 , H01R13/6585 , H01R13/6586 , H01R23/6873
Abstract: An example electronic assembly for securing an electronic card. In some forms, the electronic assembly further includes a printed circuit board. The electronic assembly includes a housing having a first set of electrical contacts and a second set of electrical contacts. The housing is configured to receive the electronic card between the first and second set of electrical contacts. The housing further includes a third set of electrical contacts and a fourth set of electrical contacts. The housing is configured to receive the electronic card between the third and fourth set of electrical contacts. A ground shield is positioned between at least one of the first and third set of electrical contacts and the second and fourth set of electrical contacts. In some forms, the ground shield may be positioned between both the first and third set of electrical contacts and the second and fourth set of electrical contacts.
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公开(公告)号:US09674954B2
公开(公告)日:2017-06-06
申请号:US13826614
申请日:2013-03-14
Applicant: Intel Corporation
Inventor: Rajasekaran Swaminathan , Donald T. Tran , Brent S. Stone , Ram Viswanath
CPC classification number: H05K1/11 , H01R12/62 , H05K1/0204 , H05K1/0298 , H05K1/111 , H05K1/117 , H05K1/181 , H05K2201/094 , H05K2201/10189 , H05K2201/10356 , H05K2201/10378 , Y02P70/611
Abstract: This disclosure relates generally to a chip package assembly arranged to be electrically coupled to a circuit board including a plurality of circuit board contacts. The chip package assembly may include a chip package including a first side and a second side, the second side including a first plurality of contacts arranged to be electrically coupled to the plurality of circuit board contacts and a second plurality of contacts arranged to be electrically coupled to a remote device via a connector assembly.
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公开(公告)号:US09640880B2
公开(公告)日:2017-05-02
申请号:US14651820
申请日:2014-07-01
Applicant: Intel Corporation
Inventor: Donald T. Tran , Jeffrey Lee , Gaurav Chawla
IPC: H01R12/53 , H01R9/03 , H01R13/6592 , H01R13/6593 , H01R13/6594
CPC classification number: H01R12/53 , H01R9/035 , H01R9/038 , H01R13/6592 , H01R13/6593 , H01R13/6594
Abstract: A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin axial cable that includes a first conductor and second conductor, a first insulator that surrounds the first conductor, and a second insulator that surrounds the second conductor. The twin axial cable further includes a ground shield that surrounds the first and second insulator. The first conductor is electrically connected to one conductive pad and the second conductor is electrically connected to another of the conductive pads. The ground shield is electrically connected to the grounding pad. A shielding structure is mounted to the substrate and is electrically connected to the grounding pad. The shielding structure includes a cap and a plurality of sidewalls extending from the cap to the substrate. The twin axial cable is positioned between the side walls.
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公开(公告)号:US20160276759A1
公开(公告)日:2016-09-22
申请号:US14651820
申请日:2014-07-01
Applicant: INTEL CORPORATION
Inventor: Donald T. Tran , Jeffrey Lee , Gaurav Chawla
IPC: H01R12/53 , H01R13/6594 , H01R13/6592 , H01R13/6593
CPC classification number: H01R12/53 , H01R9/035 , H01R9/038 , H01R13/6592 , H01R13/6593 , H01R13/6594
Abstract: A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin axial cable that includes a first conductor and second conductor, a first insulator that surrounds the first conductor, and a second insulator that surrounds the second conductor. The twin axial cable further includes a ground shield that surrounds the first and second insulator. The first conductor is electrically connected to one conductive pad and the second conductor is electrically connected to another of the conductive pads. The ground shield is electrically connected to the grounding pad. A shielding structure is mounted to the substrate and is electrically connected to the grounding pad. The shielding structure includes a cap and a plurality of sidewalls extending from the cap to the substrate. The twin axial cable is positioned between the side walls.
Abstract translation: 一种电缆连接器,包括具有多个导电焊盘和至少一个接地焊盘的衬底。 电缆连接器还包括双轴向电缆,其包括第一导体和第二导体,围绕第一导体的第一绝缘体和围绕第二导体的第二绝缘体。 双轴向电缆还包括围绕第一和第二绝缘体的接地屏蔽。 第一导体电连接到一个导电焊盘,并且第二导体电连接到另一个导电焊盘。 接地屏蔽电气连接到接地垫。 屏蔽结构安装在基板上并电连接到接地垫。 屏蔽结构包括盖和从盖到基板延伸的多个侧壁。 双轴向电缆位于侧壁之间。
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公开(公告)号:US09332643B2
公开(公告)日:2016-05-03
申请号:US13844501
申请日:2013-03-15
Applicant: INTEL CORPORATION
Inventor: Sanka Ganesan , Timothy M. Swettlen , Gary B. Long , Donald T. Tran , Jill D. Murfin , David I. Amir
CPC classification number: H01R43/0249 , H01R43/205 , H01R2107/00 , H01R2201/04 , H05K1/144 , H05K1/147 , H05K3/363 , H05K2201/042 , H05K2201/056 , H05K2201/10189 , H05K2201/1053 , H05K2201/2009
Abstract: Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the first flex cable. The assembly also includes a connector electrically coupled to the first flex cable. The first flex cable is positioned between the connector and the second flex cable. Other embodiments are described and claimed.
Abstract translation: 描述了堆叠的柔性电缆组件及其制造。 一个组件包括电耦合到第一柔性电缆的第一柔性电缆和第二柔性电缆。 组件还包括电连接到第一柔性电缆的连接器。 第一柔性电缆位于连接器和第二柔性电缆之间。 描述和要求保护其他实施例。
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