公开(公告)号：US20250125201A1

公开(公告)日：2025-04-17

申请号：US18984438

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H01L23/15 ,  H01L23/18 ,  H01L23/498 ,  H01L23/64

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. The example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.

公开(公告)号：US20250022786A1

公开(公告)日：2025-01-16

申请号：US18899851

申请日：2024-09-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Haobo Chen ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Gamba ,  Bohan Shan ,  Robert May ,  Benjamin Taylor Duong ,  Bai Nie ,  Whitney Bryks

IPC: H01L23/498 ,  H01L23/08

Abstract: Methods and apparatus for edge protected glass cores are disclosed herein. An example package substrate includes a first glass layer including a first surface, a second surface opposite the first surface, and first lateral surfaces extending between the first and second surfaces, the first glass layer having a first via extending between the first surface and the second surface; and a dielectric material in contact with the first surface of the first glass layer and in contact with the first lateral surfaces of the first glass layer.

公开(公告)号：US20240128247A1

公开(公告)日：2024-04-18

申请号：US18046635

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC: H01L25/16 ,  H01F27/02 ,  H01F27/28 ,  H01F27/29 ,  H01F41/00 ,  H01F41/04 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01F27/022 ,  H01F27/2804 ,  H01F27/292 ,  H01F41/005 ,  H01F41/041 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16235 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US11908821B2

公开(公告)日：2024-02-20

申请号：US17563995

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati ,  Hiroki Tanaka ,  Robert A. May

IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/19 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/18

Abstract: An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

公开(公告)号：US11862619B2

公开(公告)日：2024-01-02

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Robert Alan May ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Rahul N. Manepalli ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14 ,  H01L2224/1403

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20230071707A1

公开(公告)日：2023-03-09

申请号：US17470588

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Brandon C. Marin ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02F1/035

Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.

公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

公开(公告)号：US20250112100A1

公开(公告)日：2025-04-03

申请号：US18375209

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Robert May ,  Hiroki Tanaka ,  Tarek Ibrahim ,  Lilia May ,  Jason Gamba ,  Benjamin Duong ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.