公开(公告)号：US11776864B2

公开(公告)日：2023-10-03

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Edvin Cetegen ,  Nicholas Neal ,  Sergio Chan Arguedas

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/10152 ,  H01L2224/11011 ,  H01L2224/11462 ,  H01L2224/16227 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US20190198416A1

公开(公告)日：2019-06-27

申请号：US15855971

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  David W. Mendel ,  Chandra M. Jha ,  Kelly P. Lofgreen

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3737 ,  H01L23/42 ,  H01L25/0655 ,  H01L25/50

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

公开(公告)号：US11901333B2

公开(公告)日：2024-02-13

申请号：US16596367

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11901262B2

公开(公告)日：2024-02-13

申请号：US16256831

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Zhimin Wan ,  Shankar Devasenathipathy ,  Je-Young Chang

IPC: H01L23/433 ,  F28F19/01 ,  H01L21/48

CPC classification number: H01L23/4336 ,  F28F19/01 ,  H01L21/4882

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

公开(公告)号：US20200243418A1

公开(公告)日：2020-07-30

申请号：US16256831

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Zhimin Wan ,  Shankar Devasenathipathy ,  Je-Young Chang

IPC: H01L23/433 ,  H01L21/48 ,  F28F19/01

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

公开(公告)号：US20190006291A1

公开(公告)日：2019-01-03

申请号：US15635555

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/18 ,  H01L23/373 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/42 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

公开(公告)号：US12261150B2

公开(公告)日：2025-03-25

申请号：US18399189

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11832419B2

公开(公告)日：2023-11-28

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas S. Haehn ,  Je-Young Chang ,  Kyle Arrington ,  Aaron McCann ,  Edvin Cetegen ,  Ravindranath V. Mahajan ,  Robert L. Sankman ,  Ken P. Hackenberg ,  Sergio A. Chan Arguedas

IPC: H05K7/20 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

CPC classification number: H05K7/20309 ,  H01L23/3672 ,  H01L23/49816 ,  H01L24/14

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

公开(公告)号：US11594463B2

公开(公告)日：2023-02-28

申请号：US16158191

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Nicholas Haehn

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/532

Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a first layer over a second layer. The first layer may have greater thermal conductivity than the second layer. The semiconductor device package structure further includes one or more dies coupled to the substrate. A heat spreader may have a first section coupled to a first surface of a first die of the one or more dies, and a second section coupled to the first layer.

公开(公告)号：US10461011B2

公开(公告)日：2019-10-29

申请号：US15855971

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  David W. Mendel ,  Chandra M. Jha ,  Kelly P. Lofgreen

IPC: H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L23/373 ,  H01L25/065 ,  H01L25/00

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.