公开(公告)号：US20250060531A1

公开(公告)日：2025-02-20

申请号：US18938732

申请日：2024-11-06

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US20240006395A1

公开(公告)日：2024-01-04

申请号：US17853778

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma

IPC: H01L25/16 ,  H01L23/492 ,  H01L23/522 ,  H01L23/528 ,  H01L23/04 ,  H01L23/46 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L23/492 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/04 ,  H01L2224/80895 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/08146 ,  H01L23/46

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

公开(公告)号：US20230420410A1

公开(公告)日：2023-12-28

申请号：US17846129

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/46 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/46 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

公开(公告)号：US20250079398A1

公开(公告)日：2025-03-06

申请号：US18460817

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240162158A1

公开(公告)日：2024-05-16

申请号：US18055605

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Sashi Shekhar Kandanur ,  Ravindranath Vithal Mahajan ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/538 ,  B81B1/00 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B81B1/002 ,  H01L23/3121 ,  H01L23/467 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5384 ,  B81B2201/0214 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first IC die or the second IC die.

公开(公告)号：US20230420432A1

公开(公告)日：2023-12-28

申请号：US17846173

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  G02B6/42

CPC classification number: H01L25/167 ,  H01L24/08 ,  H01L23/3107 ,  H01L24/80 ,  H01L24/94 ,  G02B6/4298 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

公开(公告)号：US20230420411A1

公开(公告)日：2023-12-28

申请号：US17846153

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L25/18 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05567 ,  H01L2224/06102 ,  H01L2224/06183 ,  H01L2224/08146 ,  H01L2224/08137 ,  H01L2224/0557 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/80006

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

公开(公告)号：US20230092821A1

公开(公告)日：2023-03-23

申请号：US17482213

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Srinivas V. Pietambaram ,  Bharat Prasad Penmecha ,  Mitul Modi

IPC: G02B6/42 ,  G02B6/38

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.