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    AUTO-INCREMENT WRITE COUNT FOR NONVOLATILE MEMORY
    3.
    发明申请
    AUTO-INCREMENT WRITE COUNT FOR NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20200151052A1

    公开(公告)日：2020-05-14

    申请号：US16742332

    申请日：2020-01-14

    Applicant: Intel Corporation

    Inventor： Shekoufeh QAWAMI

    IPC: G06F11/10 ,  G06F3/06 ,  G06F9/30 ,  G06F11/07 ,  G06F9/54

    Abstract: A memory device has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array to store a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.

    CONFIGURABLE WRITE COMMAND DELAY IN NONVOLATILE MEMORY
    4.
    发明申请
    CONFIGURABLE WRITE COMMAND DELAY IN NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20200174705A1

    公开(公告)日：2020-06-04

    申请号：US16780632

    申请日：2020-02-03

    Applicant: Intel Corporation

    Inventor： Shekoufeh QAWAMI ,  Philip HILLIER ,  Benjamin GRANIELLO ,  Rajesh SUNDARAM

    IPC: G06F3/06

    Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

    EVALUATING RISK FACTORS OF PROPOSED VEHICLE MANEUVERS USING EXTERNAL AND INTERNAL DATA
    5.
    发明申请
    EVALUATING RISK FACTORS OF PROPOSED VEHICLE MANEUVERS USING EXTERNAL AND INTERNAL DATA 审中-公开

    公开(公告)号：US20190047559A1

    公开(公告)日：2019-02-14

    申请号：US16139805

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Naissa CONDE ,  Casey BARON ,  Shekoufeh QAWAMI ,  Kooi Chi OOI ,  Mengjie YU

    IPC: B60W30/095 ,  B60W50/14 ,  G05D1/00

    Abstract: Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.

    METHOD FOR NON-VOLATILE MEMORY AND MEMORY CONTROLLER SECURED AND AUTHENTICATED PAIRING
    7.
    发明申请
    METHOD FOR NON-VOLATILE MEMORY AND MEMORY CONTROLLER SECURED AND AUTHENTICATED PAIRING 审中-公开

    公开(公告)号：US20190042480A1

    公开(公告)日：2019-02-07

    申请号：US15889116

    申请日：2018-02-05

    Applicant: Intel Corporation

    Inventor： Amirali KHATIB ZADEH ,  Pavel POLIAKOV ,  Shekoufeh QAWAMI

    IPC: G06F12/14 ,  G11C29/44 ,  G06F21/44

    Abstract: Examples include techniques for determining validity of a memory used with a memory controller. Examples include a system having a memory device including a non-volatile memory and a memory controller, where the memory controller includes a validation component including a hash function and a hash table. In embodiments, the validation component performs, during a time of manufacturing of the memory controller, a test of the non-volatile memory to produce first test results, generates a first hash of the first test results using the hash function, and stores the first hash in the hash table. Later, the validation component performs, during a time of use of the memory controller after the time of manufacturing, the test of the non-volatile memory to produce second test results, generates a second hash of the second test results using the hash function, compares the first hash from the hash table with the second hash, and indicates an invalid memory when the first hash does not match the second hash.

    RANDOM NUMBER GENERATION WITH UNSTABLE BIT STATES OF NON-VOLATILE MEMORY
    8.
    发明申请
    RANDOM NUMBER GENERATION WITH UNSTABLE BIT STATES OF NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20180287793A1

    公开(公告)日：2018-10-04

    申请号：US15476739

    申请日：2017-03-31

    Applicant: INTEL CORPORATION

    Inventor： Amirali KHATIB ZADEH ,  Shekoufeh QAWAMI ,  Abhranil MAITI

    IPC: H04L9/08 ,  G11C13/00 ,  G06F12/14

    Abstract: In one embodiment, an unpredictable nature of the storage properties in what is otherwise referred to as the “lockout period” following the programming of a non-volatile bitcell in a bitcell programming interval, is advantageously utilized in a random number generation mode to read random numbers from the memory. Accordingly, instead of locking out read operations in a lockout interval, a read operation may be performed in that or a similarly placed interval to read a bit state of the bitcell, which bit state is random in nature. The instability of the storage property varies from bitcell to bitcell and therefore may be used to generate a set of random bits from a block of bitcells. Other aspects are described herein.

    FLEXIBLE DLL (DELAY LOCKED LOOP) CALIBRATION
    10.
    发明申请
    FLEXIBLE DLL (DELAY LOCKED LOOP) CALIBRATION 审中-公开

    公开(公告)号：US20170186471A1

    公开(公告)日：2017-06-29

    申请号：US14998185

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Shekoufeh QAWAMI ,  Michael J. ALLEN ,  Rajesh SUNDARAM

    IPC: G11C7/22

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C29/022 ,  G11C29/023 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2207/2254 ,  Y02D10/14

    Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

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