公开(公告)号：US06471845B1

公开(公告)日：2002-10-29

申请号：US09461849

申请日：1999-12-15

申请人： John O. Dukovic ,  William E. Corbin, Jr. ,  Erick G. Walton ,  Peter S. Locke ,  Panayotis C. Andricacos ,  James E. Fluegel ,  Evan Patton ,  Jonathan Reid

发明人： John O. Dukovic ,  William E. Corbin, Jr. ,  Erick G. Walton ,  Peter S. Locke ,  Panayotis C. Andricacos ,  James E. Fluegel ,  Evan Patton ,  Jonathan Reid

IPC分类号： C25D2112

CPC分类号： C25D21/12 ,  Y10T137/2509

摘要： A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

摘要翻译： 用于控制化学浴的组成的方法，其中使用预测剂量来解释浴的组成的变化，其中过程的操作特性被划分为多种操作模式以及相关材料的消耗或产生 根据经验确定该过程，并酌情添加材料。

公开(公告)号：US06193859B1

公开(公告)日：2001-02-27

申请号：US09074624

申请日：1998-05-07

申请人： Robert J. Contolini ,  Jonathan Reid ,  Evan Patton ,  Jingbin Feng ,  Steve Taatjes ,  John Owen Dukovic

发明人： Robert J. Contolini ,  Jonathan Reid ,  Evan Patton ,  Jingbin Feng ,  Steve Taatjes ,  John Owen Dukovic

IPC分类号： C25D1700

CPC分类号： C25D7/12 ,  C25D17/001

摘要： An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.

摘要翻译： 用于在晶片表面上沉积导电层的设备包括凸缘。 凸缘具有圆柱形壁和连接到圆柱形壁的第一端的环形空间。 在电镀过程中，环形屏蔽了晶片表面的边缘区域，从而减小了边缘区域上沉积的导电层的厚度。 此外，凸缘的圆柱形壁可以设置有与晶片相邻的多个孔，允许夹在晶片表面上的气泡容易地逸出。

公开(公告)号：US20060011483A1

公开(公告)日：2006-01-19

申请号：US11228712

申请日：2005-09-16

申请人： Steven Mayer ,  Vijay Bhaskaran ,  Evan Patton ,  Robert Jackson ,  Jonathan Reid

发明人： Steven Mayer ,  Vijay Bhaskaran ,  Evan Patton ,  Robert Jackson ,  Jonathan Reid

IPC分类号： C25D5/02

CPC分类号： C25D3/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

摘要翻译： 描述了几种用于减少或减轻在电镀微观凹陷特征的内部区域中的接缝和/或空隙的形成的技术。 阴极极化用于减轻将电镀有种子层的基板引入电镀溶液中的有害影响。 还描述了扩散控制的电镀技术，以提供沟槽和通孔的自下而上的填充，从而避免由此侧壁一起生长以产生接缝/空隙。 还描述了初步电镀步骤，在特征的内表面上镀覆导电薄膜，导致特征底部具有足够的导电性，便于自底向上填充。

公开(公告)号：US6159354A

公开(公告)日：2000-12-12

申请号：US970120

申请日：1997-11-13

申请人： Robert J. Contolini ,  Jonathan Reid ,  Evan Patton ,  Jingbin Feng ,  Steve Taatjes ,  John Owen Dukovic

发明人： Robert J. Contolini ,  Jonathan Reid ,  Evan Patton ,  Jingbin Feng ,  Steve Taatjes ,  John Owen Dukovic

IPC分类号： C25D7/12 ,  C25D5/00 ,  C25D3/38 ,  C25D5/20 ,  C25D7/04

CPC分类号： C25D7/12 ,  C25D17/001

摘要： An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.

摘要翻译： 用于在晶片表面上沉积导电层的设备包括凸缘。 凸缘具有圆柱形壁和连接到圆柱形壁的第一端的环形空间。 在电镀过程中，环形屏蔽了晶片表面的边缘区域，从而减小了边缘区域上沉积的导电层的厚度。 此外，凸缘的圆柱形壁可以设置有与晶片相邻的多个孔，允许夹在晶片表面上的气泡容易地逸出。

公开(公告)号：US08475644B2

公开(公告)日：2013-07-02

申请号：US12606030

申请日：2009-10-26

申请人： Steven Mayer ,  Jingbin Feng ,  Zhian He ,  Jonathan Reid ,  Seshasayee Varadarajan

发明人： Steven Mayer ,  Jingbin Feng ,  Zhian He ,  Jonathan Reid ,  Seshasayee Varadarajan

IPC分类号： C25D21/12 ,  C25D7/12 ,  C25D3/38

CPC分类号： C25D17/12 ,  C23C18/1601 ,  C25D5/02 ,  C25D17/001 ,  C25D17/002 ,  C25D17/007 ,  C25D17/008 ,  C25D21/12 ,  C25D21/14 ,  C25F3/30 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/6715 ,  H01L21/76873

摘要： An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

公开(公告)号：US20120279864A1

公开(公告)日：2012-11-08

申请号：US13286103

申请日：2011-10-31

申请人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

发明人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

IPC分类号： C25D5/18 ,  C25B15/02

CPC分类号： C25D3/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

摘要翻译： 描述了几种用于减少或减轻在电镀微观凹陷特征的内部区域中的接缝和/或空隙的形成的技术。 阴极极化用于减轻将电镀有种子层的基板引入电镀溶液中的有害影响。 还描述了扩散控制的电镀技术，以提供沟槽和通孔的自下而上的填充，从而避免由此侧壁一起生长以产生接缝/空隙。 还描述了初步电镀步骤，在特征的内表面上镀覆导电薄膜，导致特征底部具有足够的导电性，便于自底向上填充。

公开(公告)号：US20110221044A1

公开(公告)日：2011-09-15

申请号：US12723532

申请日：2010-03-12

申请人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

发明人： Michal Danek ,  Tom Mountsier ,  Jonathan Reid ,  Juwen Gao ,  Aaron Fellis

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.

摘要翻译： 公开了用于在铜插塞和硅之间具有插入钨层的铜填充硅通孔（TSV）的装置和方法。 方法对于具有或不具有TSV特征的镶嵌处理是有用的。 钨层用作扩散阻挡层，用于铜电解填料的种子层和减少铜和硅之间CTE引起的应力的手段。 描述了钨层对硅和铜层与钨的粘附。

公开(公告)号：US07799684B1

公开(公告)日：2010-09-21

申请号：US11682175

申请日：2007-03-05

申请人： Jonathan Reid ,  Seyang Park ,  Seshasayee Varadarajan ,  Natalia Doubina

发明人： Jonathan Reid ,  Seyang Park ,  Seshasayee Varadarajan ,  Natalia Doubina

IPC分类号： H01L21/44

CPC分类号： H01L21/76873 ,  C25D3/38 ,  C25D5/02 ,  C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/76864 ,  H01L21/76877

摘要： A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids. A plating bath nucleates copper uniformly and conformably at a high density in a very thin film. A second bath fills the features. A unique pulsed waveform enhances the nucleation density and reduces resistivity of the very thin film deposited in the nucleation operation. The process produces a thinner and conformal copper seed film than traditional PVD copper seed processes.

摘要翻译： 两步半导体电镀工艺将铜沉积在半贵金属涂层的晶片上，在晶片上均匀且无空隙。 电镀槽在非常薄的膜中以高密度均匀且顺应地使铜成核。 第二个浴缸充满了功能。 独特的脉冲波形增强了成核密度并降低了在成核操作中沉积的非常薄的薄膜的电阻率。 该方法产生比传统的PVD铜种子工艺更薄和保形的铜籽膜。

公开(公告)号：US06551483B1

公开(公告)日：2003-04-22

申请号：US09853959

申请日：2001-05-10

申请人： Steven T. Mayer ,  Jonathan Reid ,  Robert Contolini

发明人： Steven T. Mayer ,  Jonathan Reid ,  Robert Contolini

IPC分类号： C25D2112

CPC分类号： H01L21/2885 ,  C25D5/18 ,  C25D7/123

摘要： Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

摘要翻译： 控制电位电镀提供了将金属电镀到集成电路器件的高纵横比凹陷特征的表面上的有效方法。 提供了一种方法，用于减轻由于种子层与电解质溶液的接触而导致的凹陷特征上的金属种子层的腐蚀。 还可以控制电位以在种子层上提供适形电镀，并且自下而上地填充凹陷特征。 对于这些处理中的每一个，可以使用恒定的阴极电压，脉冲阴极电压或斜坡阴极电压。 用于控制电位电镀的装置包括放置在待镀表面附近的参考电极和至少一个阴极检测引线，以测量集成电路结构的圆周上的点处的电位。

公开(公告)号：US08475636B2

公开(公告)日：2013-07-02

申请号：US12481503

申请日：2009-06-09

申请人： Steven Mayer ,  Jingbin Feng ,  Zhian He ,  Jonathan Reid ,  Seshasayee Varadarajan

发明人： Steven Mayer ,  Jingbin Feng ,  Zhian He ,  Jonathan Reid ,  Seshasayee Varadarajan

IPC分类号： C25D17/12 ,  C25D21/12

CPC分类号： C25D17/12 ,  C23C18/1601 ,  C25D5/02 ,  C25D17/001 ,  C25D17/002 ,  C25D17/007 ,  C25D17/008 ,  C25D21/12 ,  C25D21/14 ,  C25F3/30 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/32125 ,  H01L21/6715 ,  H01L21/76873

摘要： An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

摘要翻译： 用于将金属层电镀到晶片表面上的装置包括位于晶片附近的离子电离离子可渗透元件和位于阳极和离子电离性可离子渗透元件之间的辅助阴极。 离子电阻性离子渗透元件用于调节晶片表面处的离子电流。 辅助阴极被配置成使来自阳极的电流分布成形。 所提供的配置有效地重新分布电镀系统中的离子电流，允许电镀均匀的金属层并减轻终端效应。