公开(公告)号：US08309447B2

公开(公告)日：2012-11-13

申请号：US12855273

申请日：2010-08-12

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Vamsi K. Paruchuri

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Vamsi K. Paruchuri

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878

摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.

摘要翻译： 公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。 该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。 因此，本公开的方法避免了短信道惩罚。 此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

公开(公告)号：US20120040522A1

公开(公告)日：2012-02-16

申请号：US12855273

申请日：2010-08-12

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Vamsi K. Paruchuri

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878

摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.

摘要翻译： 公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。 该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。 因此，本公开的方法避免了短信道惩罚。 此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

公开(公告)号：US20130344677A1

公开(公告)日：2013-12-26

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US20130341754A1

公开(公告)日：2013-12-26

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US08455932B2

公开(公告)日：2013-06-04

申请号：US13102073

申请日：2011-05-06

申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/1104 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

公开(公告)号：US20130082311A1

公开(公告)日：2013-04-04

申请号：US13609747

申请日：2012-09-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

公开(公告)号：US20130032876A1

公开(公告)日：2013-02-07

申请号：US13195153

申请日：2011-08-01

申请人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

公开(公告)号：US20110309333A1

公开(公告)日：2011-12-22

申请号：US12819440

申请日：2010-06-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/775 ,  H01L21/34 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/78696

摘要： A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

摘要翻译： 提供一种形成半导体器件的方法，其中用于源极和漏极区的掺杂剂从掺杂的介电层引入。 在一个示例中，栅极结构形成在半导体层的厚度小于10nm的SOI衬底的半导体层上。 在与栅极结构相邻的半导体层的至少一部分上形成掺杂介电层。 来自掺杂介电层的掺杂剂被驱动到与栅极结构相邻的半导体层的部分中。 扩散到半导体中的掺杂剂提供了源极和漏极延伸区域。

公开(公告)号：US08598663B2

公开(公告)日：2013-12-03

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L21/70

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US08435846B2

公开(公告)日：2013-05-07

申请号：US13251757

申请日：2011-10-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/336 ,  H01L21/461 ,  H01L29/76 ,  H01L29/66

CPC分类号： H01L29/4983 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7834

摘要： Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.

摘要翻译： 公开了晶体管器件及其制造方法。 在一种方法中，在基板上形成虚拟栅极结构。 虚拟门结构的底部是底切的。 此外，在基板上形成阶梯状，凸起的源极和漏极区域，以及由底切形成的至少一个底切部。 去除虚拟栅极结构并在衬底上形成替换栅极。