公开(公告)号：US10037952B2

公开(公告)日：2018-07-31

申请号：US15408683

申请日：2017-01-18

Applicant: MEDIATEK INC.

Inventor： Chun-Wei Chang ,  Shang-Pin Chen

IPC: H05K1/02 ,  H01L23/66 ,  H01L25/065 ,  H05K1/18 ,  H01L23/538 ,  H01L23/552 ,  G06F13/40 ,  H01L27/12 ,  H04B3/32 ,  H01L23/00 ,  H05K3/46

CPC classification number: H01L23/66 ,  G06F13/4072 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0655 ,  H01L27/12 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/3025 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/181 ,  H05K3/46 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/10318 ,  H05K2201/10522 ,  Y02D10/14 ,  Y02D10/151

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.

公开(公告)号：US11456750B2

公开(公告)日：2022-09-27

申请号：US17488339

申请日：2021-09-29

Applicant: MEDIATEK INC.

Inventor： Ang-Sheng Lin ,  Chun-Wei Chang ,  Tzu-Chan Chueh

IPC: H03L7/093 ,  H03L7/081 ,  H03L7/089 ,  H03L7/099

Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

公开(公告)号：US09978692B2

公开(公告)日：2018-05-22

申请号：US14997048

申请日：2016-01-15

Applicant: MediaTek Inc.

Inventor： PoHao Chang ,  Chun-Wei Chang ,  Ching-Chih Li

IPC: H05K1/02 ,  H01L23/552 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12 ,  H04B3/32 ,  H01L23/498 ,  H05K3/46 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/5286 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L27/12 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/3025 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K3/46

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins, and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The pins are coupled to a device via a plurality of conductive traces of a printed circuit board (PCB). The control signals control each of the driving units to selectively provide the data or one specific shielding pattern via the corresponding pin and the corresponding conductive trace of PCB to the device.

公开(公告)号：US11340641B2

公开(公告)日：2022-05-24

申请号：US16590391

申请日：2019-10-02

Applicant: MEDIATEK INC.

Inventor： Chun-Wei Chang ,  Song-Yu Yang ,  Ang-Sheng Lin

IPC: G05F1/575 ,  H03F3/45

Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.

公开(公告)号：US20220149849A1

公开(公告)日：2022-05-12

申请号：US17488339

申请日：2021-09-29

Applicant: MEDIATEK INC.

Inventor： Ang-Sheng Lin ,  Chun-Wei Chang ,  Tzu-Chan Chueh

IPC: H03L7/093 ,  H03L7/099 ,  H03L7/089 ,  H03L7/081

Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.

公开(公告)号：US20170206937A1

公开(公告)日：2017-07-20

申请号：US15297170

申请日：2016-10-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chun-Wei Chang

IPC: G11C5/04 ,  H01L23/00 ,  H01L25/10 ,  G06F13/42 ,  H01L23/31 ,  G11C14/00 ,  G11C5/06 ,  G06F13/40 ,  H01L23/538 ,  H01L25/065

CPC classification number: G11C5/04 ,  G06F13/4022 ,  G06F13/4282 ,  G06F15/7807 ,  G11C5/06 ,  G11C14/0018 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10537 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A hybrid system includes a printed circuit board (PCB) having a main surface, a package-on-package (PoP) having a bottom package mounted on the main surface of the PCB and a top package stacked on the bottom package, and a multi-chip package (MCP) on the main surface of the PCB. The bottom package includes a system-on-chip (SoC) and the top package includes at least one on-package dynamic random access memory (DRAM) die accessible to the SoC. The MCP includes at least one on-board DRAM die accessible to the SoC via a PCB trace.

公开(公告)号：US10581414B2

公开(公告)日：2020-03-03

申请号：US15274473

申请日：2016-09-23

Applicant: MediaTek Inc.

Inventor： Chun-Neng Liao ,  Meng-Hsin Chiang ,  Chun-Wei Chang ,  Chee-Kong Ung ,  Ching-Chih Li

IPC: H03K5/1252 ,  H03H7/06 ,  H01L25/16 ,  H01L23/64 ,  H03H3/02

Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.

公开(公告)号：US10271420B2

公开(公告)日：2019-04-23

申请号：US15134922

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： PoHao Chang ,  Chun-Wei Chang

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H05K1/02 ,  H05K1/09

Abstract: An electronic apparatus is provided. The electronic apparatus includes a printed circuit board (PCB) with a first signal path and a second signal path therein, a first finger disposed on the first signal path, a second finger disposed on the second signal path, a controller disposed on the PCB and coupled to a first memory via the first finger and to a second memory via the second finger, and a damping device disposed on the second signal path. The first and second signal paths share a common segment between the controller and a branch point on the PCB. The damping device is disposed between the second finger and the branch point. The distance between the first finger and the branch point within the first signal path is smaller than the distance between the second finger and the branch point within the second signal path.

公开(公告)号：US20160218092A1

公开(公告)日：2016-07-28

申请号：US14920883

申请日：2015-10-23

Applicant: Mediatek Inc.

Inventor： Po-Hao Chang ,  Chun-Wei Chang ,  Ching-Chih Li

IPC: H01L25/16 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/19104 ,  H01L2924/19105

Abstract: A chip package includes a first die encapsulated by a molding compound; a board comprising a chip mounting surface; a redistributed layer (RDL) structure on an active surface of the first die and between the die and the chip mounting surface; and a discrete passive device embedded in the molding compound and situated in close proximity to a side edge of the first die.

Abstract translation: 芯片封装包括由模塑料封装的第一模具; 包括芯片安装表面的板; 在所述第一管芯的有效表面上以及所述管芯和所述芯片安装表面之间的再分布层（RDL）结构; 以及嵌入在模制化合物中且位于第一模具的侧边缘附近的分立无源器件。