公开(公告)号：US20240061592A1

公开(公告)日：2024-02-22

申请号：US18231338

申请日：2023-08-08

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Jonathan S. Parry ,  Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu ,  Jeremy Binfet ,  Walter Di Francesco ,  Daniel J. Hubbard ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F1/3234

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F1/3275

Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

公开(公告)号：US11775185B2

公开(公告)日：2023-10-03

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5018

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US10936210B2

公开(公告)日：2021-03-02

申请号：US16506020

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Dheeraj Srinivasan ,  Terry M. Grunzke

IPC: G06F3/06 ,  G06F12/0811

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

公开(公告)号：US20210057031A1

公开(公告)日：2021-02-25

申请号：US17090067

申请日：2020-11-05

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

IPC: G11C16/08 ,  G11C16/12 ,  G06F3/06 ,  G11C8/08

Abstract: The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

公开(公告)号：US09514829B2

公开(公告)日：2016-12-06

申请号：US14958217

申请日：2015-12-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Benjamin Louie ,  Ali Mohammadzadeh ,  Aaron S. Yip

IPC: G11C5/14 ,  G11C16/24 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

公开(公告)号：US12271592B2

公开(公告)日：2025-04-08

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G11C13/00 ,  G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

公开(公告)号：US11861228B2

公开(公告)日：2024-01-02

申请号：US17514267

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Ali Mohammadzadeh ,  Dheeraj Srinivasan ,  Daniel J. Hubbard ,  Luca Bert

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673

Abstract: Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

公开(公告)号：US20210103389A1

公开(公告)日：2021-04-08

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20200167229A1

公开(公告)日：2020-05-28

申请号：US16776600

申请日：2020-01-30

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C8/12

Abstract: The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

公开(公告)号：US20190332284A1

公开(公告)日：2019-10-31

申请号：US16506020

申请日：2019-07-09

Applicant: Micron Technology, Inc.

Inventor： Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Dheeraj Srinivasan ,  Terry M. Grunzke

IPC: G06F3/06 ,  G06F12/0811

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.