公开(公告)号：US5243205A

公开(公告)日：1993-09-07

申请号：US899123

申请日：1992-06-18

申请人： Mitsuhiko Kitagawa ,  Tetsujiro Tsunoda ,  Akihiko Osawa

发明人： Mitsuhiko Kitagawa ,  Tetsujiro Tsunoda ,  Akihiko Osawa

IPC分类号： H01L21/263 ,  H01L29/32 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L31/111

CPC分类号： H01L31/1113 ,  H01L21/263 ,  H01L29/32 ,  H01L29/7395 ,  H01L29/7424 ,  H01L29/7802 ,  H01L29/41766

摘要： In a photothyristor, a main thyristor consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed on a semiconductor substrate. Also a pilot thyristor surrounded with the main thyristor and consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed. In the P gate base layer, a trigger light irradiation surface including the inner surface of a recess is formed on the center of the pilot thyristor. In the N base layer, a crystal defect layer is formed under the trigger light irradiation surface by the irradiation with a radiant ray. A breakdown voltage to protect the thyristor from overvoltage is controlled by the crystal defect layer.

摘要翻译： 在光闸晶体管中，在半导体衬底上形成由P发射极层，N基极层，P栅极基极层和N发射极层构成的主晶闸管。 另外，由主晶闸管包围并由P发射极层，N基极层，P栅极基极层和N发射极层构成的导频晶闸管。 在P栅极基极层中，在导频晶闸管的中心形成有包括凹部的内表面的触发光照射面。 在N基层中，通过用辐射线照射在触发光照射面下形成晶体缺陷层。 用于保护晶闸管的过电压的击穿电压由晶体缺陷层控制。

公开(公告)号：US5250446A

公开(公告)日：1993-10-05

申请号：US959465

申请日：1992-10-09

申请人： Akihiko Osawa ,  Yoshiro Baba ,  Mitsuhiko Kitagawa ,  Tetsujiro Tsunoda

发明人： Akihiko Osawa ,  Yoshiro Baba ,  Mitsuhiko Kitagawa ,  Tetsujiro Tsunoda

IPC分类号： H01L21/322 ,  H01L21/265 ,  H01L29/32

CPC分类号： H01L21/263 ,  H01L21/26506 ,  H01L29/32 ,  Y10S148/128

摘要： A mixture of at least two types of charged particles of ions having the same value obtained by dividing the electric charge of an ion by the mass of the ion, i.e., a mixture of charged particles including hydrogen molecular ions H.sub.2.sup.+ and deuterium ions D.sup.+, is accelerated in a charged particle accelerator. Since the mass spectrograph unit in the accelerator cannot divide the hydrogen molecular ions H.sub.2.sup.+ and the deuterium ion D.sup.+, both ions are accelerated together. When the hydrogen molecular ion H.sub.2.sup.+ collides against a silicon substrate, it is divided into two hydrogen ions 2H.sup.+. Since the hydrogen ion H.sup.+ and the deuterium ion D.sup.+ have different ranges in silicon, two regions including a great number of crystal defects are formed in the silicon substrate in one ion irradiating step. As a result, at least three regions of different lifetimes of carriers are formed at different depths of the semiconductor substrate.

摘要翻译： 将离子电荷除以离子质量，即包含氢分子离子H 2 +和氘离子D +的带电粒子的混合物获得的具有相同值的至少两种类型的带电粒子的混合物是 在带电粒子加速器中加速。 由于加速器中的质谱仪单元不能分离氢分子离子H2 +和氘离子D +，所以两个离子一起被加速。 当氢分子离子H2 +碰撞硅衬底时，它被分为两个氢离子2H +。 由于氢离子H +和氘离子D +在硅中具有不同的范围，因此在一个离子照射步骤中在硅衬底中形成包括大量晶体缺陷的两个区域。 结果，在半导体衬底的不同深度形成载流子寿命不同的至少三个区域。

公开(公告)号：US6084263A

公开(公告)日：2000-07-04

申请号：US27727

申请日：1998-02-23

申请人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

发明人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

IPC分类号： H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7395 ,  H01L29/0611

摘要： The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.

摘要翻译： 本发明的主要特征是当具有高击穿电压的平面型半导体器件被反向偏置时，防止漏电流流动。 例如，在n型Si衬底的表面上形成半导体膜，该第二p型基极层选择性地形成在Si衬底表面上的第二p型基极层和形成为围绕第二p型基极层的沟道阻挡层 以预定间隔。 半导体膜的悬挂键密度设定为1.25×10 18 cm -3。 利用这种结构，带隙中的离散水平接近连续体，缩短了用载体填充半导体薄膜中的捕获水平所需的时间。

公开(公告)号：US5731637A

公开(公告)日：1998-03-24

申请号：US687032

申请日：1996-07-25

申请人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

发明人： Shizue Hori ,  Akihiko Osawa ,  Yoshiro Baba ,  Shigeo Yawata

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/322 ,  H01L21/332 ,  H01L29/08 ,  H01L23/58

CPC分类号： H01L29/66363 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3221 ,  H01L29/083

摘要： The object of the present invention is to provide a method of manufacturing high-performance, high-breakdown-voltage semiconductor devices which suppresses an increase in the junction leakage current due to heavy metal contamination without increasing the number of manufacturing steps. A method of manufacturing semiconductor devices according to the invention, comprises the steps of ion-implanting one or more elements selected from a group of silicon, carbon, nitrogen, oxygen, hydrogen, argon, helium, and xenon into at least one surface of a semiconductor substrate of a first conductivity type at a dose of 1.times.10.sup.15 cm.sup.-2 or more to form a distortion layer, oxidizing the surface of the substrate to form an oxide film, ion-implanting impurities of a second conductivity type at a low concentration (a dose of less than 1.times.10.sup.15 cm.sup.-2) via the oxide film into the one surface of the substrate, ion-implanting impurities of the second conductivity type at a high concentration (a dose of 1.times.10.sup.15 cm.sup.-2 or more) via the oxide film into the other surface of the substrate, and forming a junction by heat treatment.

摘要翻译： 本发明的目的是提供一种制造高性能，高耐击穿电压半导体器件的方法，其抑制由于重金属污染导致的结漏电流的增加，而不增加制造步骤的数量。 根据本发明的制造半导体器件的方法包括以下步骤：将选自硅，碳，氮，氧，氢，氩，氦和氙的一种或多种元素离子注入至 以1×10 15 cm -2以上的剂量的第一导电类型的半导体衬底形成失真层，氧化衬底的表面以形成氧化膜，以低浓度离子注入第二导电类型的杂质（a 通过该氧化膜将该剂量小于1×10 15 cm -2）通过氧化膜以高浓度（1×10 15 cm -2以上的剂量）将第二导电型的杂质离子注入到 衬底的另一个表面，并通过热处理形成结。

公开(公告)号：US07227223B2

公开(公告)日：2007-06-05

申请号：US10618624

申请日：2003-07-15

申请人： Noboru Matsuda ,  Hitoshi Kobayashi ,  Masaru Kawakatsu ,  Akihiko Osawa

发明人： Noboru Matsuda ,  Hitoshi Kobayashi ,  Masaru Kawakatsu ,  Akihiko Osawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7802

摘要： A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end. The second spacing is greater than the first spacing.

摘要翻译： 一种半导体器件，特别是MOS晶体管器件，其中为了增加沟道区密度并实现晶体管器件的低电阻，提供了一种第一栅极电极组，其具有形成在半导体衬底上的多个栅极电极 在第一等间隔处彼此远离的第二栅极电极组，具有形成在半导体衬底上的多个栅电极以彼此间隔开的第一等间距彼此远离的第二栅电极组;远离第一或第二 第二间隔的栅极电极组和用于将第一栅极电极组和源极接触电互连的源极区域。 源极区域在第一栅电极组的一端彼此连接，并在第一栅电极组的另一端分离。 此外，第一组的栅电极在另一端彼此连接。 第二个间距大于第一个间距。

公开(公告)号：US06740931B2

公开(公告)日：2004-05-25

申请号：US10417110

申请日：2003-04-17

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696

摘要： A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

公开(公告)号：US06239464B1

公开(公告)日：2001-05-29

申请号：US09226720

申请日：1999-01-07

申请人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Masanobu Tsuchitani ,  Keita Suzuki ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L29792

CPC分类号： H01L29/66666 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device, which can have a uniform film on open ends of trenches by using materials having a different oxidation rate, and a fabrication method thereof are provided. The semiconductor device having trenches configured to have open ends covered with an oxidation film made of a material having an oxidation rate faster than that of a semiconductor substrate and a fabrication method thereof are provided.

摘要翻译： 提供一种半导体器件及其制造方法，该半导体器件可以通过使用具有不同氧化速率的材料在沟槽的开口端上具有均匀的膜。 具有沟槽的半导体器件被配置为具有用氧化速率快于半导体衬底的材料制成的氧化膜覆盖的开口端及其制造方法。

公开(公告)号：US6010950A

公开(公告)日：2000-01-04

申请号：US026508

申请日：1998-02-19

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba

IPC分类号： H01L21/02 ,  H01L21/18 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/18 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76251 ,  H01L21/76264

摘要： The most distinctive feature of the present invention lies in that a warp and crystal defects can be prevented from occurring and a processing margin for forming an isolation groove can be improved in an intelligent power device including a power element section and an IC control section within one chip. A bonded wafer is obtained by bonding an active-layer substrate and a supporting substrate with an epitaxially grown silicon layer interposed therebetween so as to cover an oxide film selectively formed at the interface of the active-layer substrate. Isolation trenches are then formed in the bonded wafer to such a depth as to reach the oxide film from the element forming surface of the active-layer substrate. Thus, an IC controller is formed within a dielectric isolation region surrounded with the isolation trenches and the oxide film and accordingly the IC controller can effectively be isolated by a dielectric.

摘要翻译： 本发明的最显着的特征在于，可以防止发生翘曲和晶体缺陷，并且可以在包括功率元件部分和IC控制部分的智能功率器件的一个智能功率器件内改善用于形成隔离沟槽的加工余量 芯片。 通过将有源层衬底和支撑衬底与外延生长的硅层接合以便覆盖在有源层衬底的界面处有选择地形成的氧化物膜而获得接合晶片。 然后在接合的晶片中形成隔离沟槽到从活性层衬底的元件形成表面到达氧化物膜的深度。 因此，在由隔离沟槽和氧化物膜包围的电介质隔离区域内形成IC控制器，因此可以通过电介质来有效地隔离IC控制器。

公开(公告)号：US4984052A

公开(公告)日：1991-01-08

申请号：US418587

申请日：1989-10-10

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S257/914

摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

摘要翻译： 键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层， 在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。 半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。

公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。