公开(公告)号：US20180053740A1

公开(公告)日：2018-02-22

申请号：US15243923

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Manoj KAKADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/15313 ,  H05K1/111 ,  H05K1/185 ,  H05K2201/09472

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

公开(公告)号：US20160066414A1

公开(公告)日：2016-03-03

申请号：US14474860

申请日：2014-09-02

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming JOW ,  Young Kyu SONG ,  Jung Ho YOON ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H05K1/02 ,  H01L23/522 ,  H05K1/18 ,  H01L21/48 ,  H05K1/11 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L23/5286 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括第一体层，可包括位于第一体层上方的一个或多个电感器，耦合电感器或电感元件的变压器。 第一接地平面位于第一体层和感应元件之间的第一体层的顶部。 第一接地平面可以具有大致垂直于由感应元件产生的磁场的导线，以及与第一接地平面相对的第一体层底部的第二接地平面。 第一和第二接地平面还可以为半导体提供散热元件，以及减少或消除由电感元件产生的涡流和寄生效应。

公开(公告)号：US20190043817A1

公开(公告)日：2019-02-07

申请号：US16132315

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Manoj KADADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

公开(公告)号：US20160240606A1

公开(公告)日：2016-08-18

申请号：US14625484

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming JOW ,  Young Kyu SONG ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Abstract translation: 上平面电容器通过电介质层在下平面电容器之上隔开。 桥接后层间连接器通过第一柱和第二柱并联耦合电容。 第一柱和第二柱延伸穿过介电层，邻近上下平面电容器。 第一级耦合器延伸在介电层下方并将第一柱连接在一起并连接到下平面电容器的导体，并将下平面电容器的另一导体耦合到第二柱之一。 第二级耦合器延伸在电介质层上方，并将第二柱耦合到上平面电容器的导体，并将上平面电容器的另一导体耦合到第一柱之一。

公开(公告)号：US20160172274A1

公开(公告)日：2016-06-16

申请号：US14572760

申请日：2014-12-16

Applicant: Qualcomm Incorporated

Inventor： Jung Ho YOON ,  Young Kyu SONG ,  Uei-Ming JOW ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.

Abstract translation: 根据一些示例的半导体封装可以包括被配置为RF信号连接的支撑板的第一部分，热耦合到支撑板的第二部分以散热的半导体管芯，第一再分配层位于 第二再分布层，以将第一再分布层电容耦合到第二再分配层，在第一部分和第一再分布层之间延伸的第一通孔，以及紧邻第一通孔的第二通孔，以将第二通孔电容耦合到第一通路 通过。

公开(公告)号：US20150228707A1

公开(公告)日：2015-08-13

申请号：US14179202

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Yunseo PARK ,  Xiaonan ZHANG ,  Ryan David LANE ,  Aristotele HADJICHRISTOS

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/3192 ,  H01L23/5227 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/16225 ,  H01L2924/01029 ,  H01L2924/30107

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract translation: 晶圆级封装（WLP）上的电感器设计不需要将焊球沉淀在芯片上，因为焊球形成电感器的一部分。 电感器上的一个端子耦合到管芯，另一个端子耦合到管芯上的单个焊球，并且与电感器机械接触的剩余焊球保持电浮动。 所产生的器件具有更好的电感，直流（DC）电阻，电路板级可靠性（BLR）和品质因数（Q）。