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公开(公告)号：US11469194B2
公开(公告)日：2022-10-11
申请号：US16535029
申请日：2019-08-07
发明人： Paolo Colpani , Samuele Sciarrillo , Ivan Venegoni , Francesco Maria Pipia , Simone Bossi , Carmela Cupeta
IPC分类号： H01L23/00 , H01L21/768 , H01L23/528 , H01L21/02
摘要： A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.
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2.发明申请公开(公告)号：US20180182864A1
公开(公告)日：2018-06-28
申请号：US15595256
申请日：2017-05-15
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/40
CPC分类号： H01L29/66734 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02645 , H01L21/265 , H01L21/48 , H01L21/743 , H01L23/3178 , H01L29/401 , H01L29/4236 , H01L29/7802 , H01L29/7809
摘要： A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.
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公开(公告)号：US12021046B2
公开(公告)日：2024-06-25
申请号：US17944983
申请日：2022-09-14
发明人： Paolo Colpani , Samuele Sciarrillo , Ivan Venegoni , Francesco Maria Pipia , Simone Bossi , Carmela Cupeta
IPC分类号： H01L23/00 , H01L21/02 , H01L21/768 , H01L23/528
CPC分类号： H01L24/03 , H01L21/02164 , H01L21/0217 , H01L21/76802 , H01L21/76877 , H01L23/528 , H01L24/05 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/024 , H01L2224/03464 , H01L2224/03614 , H01L2224/04042 , H01L2224/05024 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05664 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/0132 , H01L2924/05042 , H01L2924/05442 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107
摘要： A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.
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4.发明授权公开(公告)号：US09640614B2
公开(公告)日：2017-05-02
申请号：US14509229
申请日：2014-10-08
IPC分类号： H01L29/78 , H01L29/51 , H01L29/06 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/66
CPC分类号： H01L29/0653 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.
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5.发明申请INTEGRATED DEVICE WITH RAISED LOCOS INSULATION REGIONS AND PROCESS FOR MANUFACTURING SUCH DEVICE 审中-公开具有增加的LOCOS绝缘区域的集成装置和用于制造这种装置的方法公开(公告)号：US20150054088A1
公开(公告)日：2015-02-26
申请号：US14509229
申请日：2014-10-08
IPC分类号： H01L29/06
CPC分类号： H01L29/0653 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L29/42368 , H01L29/66681 , H01L29/7816
摘要： An integrated device includes a semiconductor body including an STI insulating structure that laterally delimits first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. A power component, formed in the second active area, includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region. The insulating region is arranged between the body region and the drain-contact region and has a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion.
摘要翻译： 集成器件包括分别在半导体本体的低电压区域和功率区域中横向限定第一有源区和至少一个第二有源区的STI绝缘结构的半导体本体。 低压CMOS元件容纳在第一个有源区域中。 形成在第二有源区域中的功率部件包括源极区域，主体区域，漏极接触区域以及至少一个LOCOS绝缘区域。 绝缘区域布置在体区域和漏极 - 接触区域之间，并且具有从半导体主体的表面露出的突出部分和其内部的嵌入部分。 LOCOS绝缘区域的突出部分的体积大于嵌入部分的体积。
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公开(公告)号：US11587866B2
公开(公告)日：2023-02-21
申请号：US17000165
申请日：2020-08-21
发明人： Francesco Maria Pipia , Ivan Venegoni , Annamaria Votta , Francesca Milanesi , Samuele Sciarrillo , Paolo Colpani
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L23/528 , H01L23/525
摘要： A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.
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公开(公告)号：US10593625B2
公开(公告)日：2020-03-17
申请号：US16048123
申请日：2018-07-27
IPC分类号： H01L23/00 , H01L23/532 , H01L23/538 , H01L21/308 , H01L21/768 , H01L23/528 , H01L23/31 , H01L23/29 , H01L23/525
摘要： A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.
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公开(公告)号：US10566283B2
公开(公告)日：2020-02-18
申请号：US16048108
申请日：2018-07-27
发明人： Samuele Sciarrillo , Paolo Colpani , Ivan Venegoni
IPC分类号： H01L23/528 , H01L23/532 , H01L21/768 , H01L23/31 , H01L23/00 , H01L23/525
摘要： A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.
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公开(公告)号：US10141422B2
公开(公告)日：2018-11-27
申请号：US15595256
申请日：2017-05-15
IPC分类号： H01L29/76 , H01L29/66 , H01L21/02 , H01L21/74 , H01L29/78 , H01L29/40 , H01L29/423 , H01L21/48
摘要： A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.
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公开(公告)号：US10790226B2
公开(公告)日：2020-09-29
申请号：US16044186
申请日：2018-07-24
发明人： Francesco Maria Pipia , Ivan Venegoni , Annamaria Votta , Francesca Milanesi , Samuele Sciarrillo , Paolo Colpani
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L23/528 , H01L23/525
摘要： An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.
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