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公开(公告)号：US20240274173A1
公开(公告)日：2024-08-15
申请号：US18498267
申请日：2023-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Cheolhui LEE , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC classification number: G11C7/222 , G11C7/1081 , G11C7/14 , G11C7/225
Abstract: Provided is a nonvolatile memory including a receive buffer configured to generate a buffer signal by comparing an input signal with a reference voltage, a reference voltage calibrator configured to generate a calibrated reference voltage code signal based on a reference voltage code signal and the buffer signal, and a reference voltage generator configured to generate a reference voltage corresponding to the calibrated reference voltage code signal. In addition, the read reference voltage calibrator includes a duty cycle monitor configured to generate a monitoring signal by measuring a duty cycle of the buffer signal, an up/down counter configured to generate a count number signal by comparing a reference duty cycle with a measurement duty cycle corresponding to the monitoring signal, and a code calculator configured to generate the calibrated reference voltage code signal based on the count number signal and the reference voltage code signal.
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公开(公告)号：US20240321866A1
公开(公告)日：2024-09-26
申请号：US18614152
申请日：2024-03-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyunsuk KANG , Jehoon KIM , Jungjune PARK , Chiweon YOON
CPC classification number: H01L27/0285 , H02H9/046
Abstract: An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.
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公开(公告)号：US20240221846A1
公开(公告)日：2024-07-04
申请号：US18465541
申请日：2023-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chihyun KIM , Junehong PARK , Jayang YOON , Chiweon YOON , Hyeongdo CHOI
CPC classification number: G11C16/3427 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
Abstract: In a method of operating a memory device, a first operation is performed on a memory block by applying first driving voltages to a plurality of wordlines. After the first operation is completed, a first recovery operation in which the first driving voltages applied to the plurality of wordlines are discharged is performed. After the first recovery operation is completed, a second operation is performed on the memory block by applying second driving voltages to the plurality of wordlines. In the first recovery operation, first charges among a plurality of charges stored by the first driving voltages are stored in a charge recycling memory block connected to at least one charge recycling wordline. In the second operation, the second driving voltages are applied to the plurality of wordlines using the first charges stored in the charge recycling memory block.
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公开(公告)号：US20240274212A1
公开(公告)日：2024-08-15
申请号：US18241621
申请日：2023-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yumin KIM , Jungyu LEE , Jihyun PARK , Chiweon YOON , Eunchan LEE
CPC classification number: G11C29/12005 , G11C7/04 , G11C29/028 , G11C29/1201
Abstract: A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.
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公开(公告)号：US20240203499A1
公开(公告)日：2024-06-20
申请号：US18468345
申请日：2023-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Philkyu KANG , Chihyun KIM , Junehong PARK , Jayang YOON , Chiweon YOON , Dojeon LEE
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/24 , G11C16/30
Abstract: Provided is a method of operating a nonvolatile memory device including a voltage generator, the method including calculating a difference between a voltage level of a first word line node and a voltage level of a second word line node, changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the voltage levels, and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level. The first word line node may be closer from an output terminal of the voltage generator than the second word line node.
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Patent Agency Ranking
公开(公告)号：US20200321349A1
公开(公告)日：2020-10-08
申请号：US16662073
申请日：2019-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehong KWON , Chanho KIM , Daeseok BYEON , Pansuk KWAK , Chiweon YOON
IPC: H01L27/11573 , H01L27/11582 , H01L29/94 , H01L29/78
Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.
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7.发明公开公开(公告)号：US20240257848A1
公开(公告)日：2024-08-01
申请号：US18494258
申请日：2023-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwanseok KU , Youngmin JO , Anil KAVALA , Jungjune PARK , Chiweon YOON
CPC classification number: G11C7/222 , G11C7/1057 , G11C8/18
Abstract: A memory package includes a data input/output pin, a data strobe pin, a plurality of memory devices, and a buffer device. The data input/output pin receives a data signal. The data strobe pin receives a data strobe signal. The plurality of memory devices operate based on the data signal and the data strobe signal. The buffer device is between the data input/output pin, the data strobe pin and the plurality of memory devices, and performs a training operation based on training data and the data strobe signal in response to the data signal including the training data and the data strobe signal being received. During the training operation, the buffer device sets different delays on a plurality of sub-training data included in the training data, and the sub-training data on which the different delays are set are stored in different memory regions of the plurality of memory devices.
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公开(公告)号：US20240257843A1
公开(公告)日：2024-08-01
申请号：US18230951
申请日：2023-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor： Jihyun PARK , Jungyu LEE , Yumin KIM , Chiweon YOON , Eunchan LEE
CPC classification number: G11C7/02 , G11C7/1057 , G11C7/14
Abstract: The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.
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9.发明公开公开(公告)号：US20240204760A1
公开(公告)日：2024-06-20
申请号：US18239589
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joonyoung KIM , Sanglok KIM , Jungjune PARK , Chiweon YOON
IPC: H03K3/3562 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/32
CPC classification number: H03K3/35625 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32
Abstract: A data flip-flop circuit includes a flip-flop, a recovery latch and a cut-off transistor. The flip-flop stores a data signal that is input, using a clock signal and a virtual power supply voltage and provides the stored data signal as an output signal at an output node in response to a rising transition of the clock signal. The recovery latch is connected to a power supply voltage and a ground voltage, is connected to the flip-flop at the output node, stores the output signal internally in response to a first transition of a chip enable signal, recovers the stored output signal in response to end of a power gating interval based on the chip enable signal, and provides the recovered output signal to the flip-flop. The cut-off transistor floats the virtual power supply voltage provided to the flip-flop based on a first power gating signal.
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公开(公告)号：US20240096382A1
公开(公告)日：2024-03-21
申请号：US18464618
申请日：2023-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tongsung KIM , Junghwan KWAK , Seungjun BAE , Chiweon YOON , Byungkwan CHUN , Youngmin JO
CPC classification number: G11C7/1048 , G06F13/16 , G06F2213/16 , G11C2207/2254
Abstract: A ZQ calibration circuit includes: a ZQ controller configured to detect an end of one interface mode, among a plurality of interface modes in which ZQ calibration is supported, and to instruct a switch to another interface mode in response to the one interface mode coming to an end; a ZQ engine configured to generate a first reference voltage corresponding to the one interface mode through a multi-reference voltage generator, to generate a second reference voltage corresponding to the another interface mode in response to the switch to the another interface mode being instructed, to perform the ZQ calibration based on the first reference voltage or the second reference voltage, and to output a calibration code; and a ZQ driver configured to output an output signal through an input/output pad based on the calibration code.
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