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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11699992B2

    公开(公告)日：2023-07-11

    申请号：US16726379

    申请日：2019-12-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

    IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

    CPC classification number: H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

    Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

    INTEGRATED CIRCUIT INCLUDING CONNECTION LINE
    2.
    发明申请
    INTEGRATED CIRCUIT INCLUDING CONNECTION LINE 有权

    公开(公告)号：US20220189945A1

    公开(公告)日：2022-06-16

    申请号：US17545009

    申请日：2021-12-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeha Lee ,  Jintae Kim ,  Keunho Lee ,  Dongyeon Heo

    IPC: H01L27/02 ,  G06F30/392

    Abstract: An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line.

    SEMICONDUCTOR DEVICES HAVING STANDARD CELLS THEREIN WITH IMPROVED INTEGRATION AND RELIABILITY
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING STANDARD CELLS THEREIN WITH IMPROVED INTEGRATION AND RELIABILITY 有权

    公开(公告)号：US20210343699A1

    公开(公告)日：2021-11-04

    申请号：US17147567

    申请日：2021-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jintae Kim ,  Jaeha Lee ,  Dongyeon Heo

    IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/394

    Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length.

    LEVEL SHIFTING CIRCUIT
    4.
    发明申请
    LEVEL SHIFTING CIRCUIT 审中-公开

    公开(公告)号：US20170117898A1

    公开(公告)日：2017-04-27

    申请号：US15285348

    申请日：2016-10-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dalhee Lee ,  Jintae Kim ,  Jaeha Lee

    IPC: H03K19/0185

    CPC classification number: H03K19/018521

    Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

    INTEGRATED CIRCUIT DEVICES INCLUDING LOWER INTERCONNECT METAL LAYERS AT CELL BOUNDARIES AND METHODS OF FORMING THE SAME
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING LOWER INTERCONNECT METAL LAYERS AT CELL BOUNDARIES AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20250105153A1

    公开(公告)日：2025-03-27

    申请号：US18752851

    申请日：2024-06-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jintae Kim ,  Panjae Park ,  Kang-Ill Seo

    IPC: H01L23/528 ,  H01L23/48 ,  H01L27/092

    Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

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