公开(公告)号：US20180040658A1

公开(公告)日：2018-02-08

申请号：US15583224

申请日：2017-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Yungcheol KONG ,  Hyunsu JUN ,  Kyoungsei CHOI

IPC: H01L27/146 ,  H01L23/00 ,  H01L31/024

CPC classification number: H01L27/14634 ,  H01L24/48 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/1469 ,  H01L31/0203 ,  H01L31/024 ,  H01L2224/16227

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US20220302035A1

公开(公告)日：2022-09-22

申请号：US17835768

申请日：2022-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jungwoo KIM ,  Jihwang KIM ,  Jongbo SHIM ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US20200303445A1

公开(公告)日：2020-09-24

申请号：US16898610

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Yungcheol KONG ,  Hyunsu JUN ,  Kyoungsei CHOI

IPC: H01L27/146 ,  H01L31/0203 ,  H01L23/00 ,  H01L31/024

Abstract: A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

公开(公告)号：US20190139899A1

公开(公告)日：2019-05-09

申请号：US16240174

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US20190206832A1

公开(公告)日：2019-07-04

申请号：US16295276

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Yungcheol KONG ,  Kyoungsei CHOI

IPC: H01L25/04 ,  H01L27/146 ,  H01L23/49 ,  H01L23/528

Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

公开(公告)号：US20180040584A1

公开(公告)日：2018-02-08

申请号：US15469837

申请日：2017-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung KANG ,  Yungcheol KONG ,  Kyoungsei CHOI

IPC: H01L25/04 ,  H01L23/49 ,  H01L27/146 ,  H01L23/528

CPC classification number: H01L25/043 ,  H01L23/49 ,  H01L23/528 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14665 ,  H01L2224/73204

Abstract: Provided are a stacked image sensor package and a packaging method thereof. A stacked image sensor package includes: a stacked image sensor in which a pixel array die and a logic die are stacked; a redistribution layer formed on one surface of the stacked image sensor, rerouting an input/ output of the stacked image sensor, and including a first pad and a second pad; a memory die connected with the first pad of the redistribution layer and positioned on the stacked image sensor; and external connectors connected with the second pad, connecting the memory die and the stacked image sensor with an external device, and having the memory die positioned therebetween.

公开(公告)号：US20140239477A1

公开(公告)日：2014-08-28

申请号：US14272681

申请日：2014-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsuk KIM ,  Jangwoo LEE ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/06 ,  H01L23/34 ,  H01L23/552

CPC classification number: H01L23/06 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16251 ,  H01L2924/00

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract translation: 一种半导体封装，包括具有芯片安装区域和周边区域的封装基板，并且包括形成在周边区域中的接地层，在芯片安装区域中的封装基板上的第一焊球，接地层上的第二焊球，至少 可以提供在芯片安装区域中堆叠在封装基板上的一个半导体芯片，以及覆盖半导体芯片并且在周边区域中与封装基板接触的封装帽。 封装帽电连接到第二焊球。 还提供了制造半导体封装的方法。

公开(公告)号：US20140184312A1

公开(公告)日：2014-07-03

申请号：US14196602

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Eunseok CHO ,  Mi-Na CHOI ,  Kyoungsei CHOI ,  Heejung HWANG ,  Seran BAE

IPC: G05F1/46

CPC classification number: G05F1/463 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00

Abstract: An example embodiment relates to a semiconductor device including a semiconductor package in which a semiconductor chip is mounted on the package substrate. The semiconductor package may include a temperature measurement device and a temperature control circuit. The temperature measurement device may measure a temperature of the semiconductor package. The temperature control circuit may change an operation speed of the semiconductor package on the basis of the temperature of the semiconductor package measured by the temperature measurement device.

Abstract translation: 示例性实施例涉及一种包括半导体封装的半导体器件，其中半导体芯片安装在封装衬底上。 半导体封装可以包括温度测量装置和温度控制电路。 温度测量装置可以测量半导体封装的温度。 温度控制电路可以基于由温度测量装置测量的半导体封装的温度来改变半导体封装的操作速度。

公开(公告)号：US20160329285A1

公开(公告)日：2016-11-10

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.