Abstract:
A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
Abstract:
An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.
Abstract:
A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.
Abstract:
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.
Abstract:
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.
Abstract:
An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.
Abstract:
An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.
Abstract:
Provided is a printed circuit board (PCB). The PCB includes a board body that includes a first surface and a second surface opposite the first surface, a semiconductor chip mounting region that is disposed on the first surface of the board body, and includes a plurality of semiconductor chip mounting parts on which a semiconductor chip may be mounted, a through region that is disposed at a peripheral portion of the semiconductor chip mounting region, and includes a plurality of through holes passing through the board body, and an external terminal forming region that is disposed on the second surface of the board body, wherein a plurality of external terminal forming parts are disposed at the external terminal forming region in correspondence with the respective semiconductor chip mounting parts.
Abstract:
A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.
Abstract:
A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.