公开(公告)号：US12262641B2

公开(公告)日：2025-03-25

申请号：US17466246

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungil Hong ,  Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Heeju Shin ,  Se Chung Oh

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

公开(公告)号：US20190140163A1

公开(公告)日：2019-05-09

申请号：US16021708

申请日：2018-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjun Yun ,  Sang-Kuk Kim ,  Jae Hoon Kim ,  Eunsun Noh ,  Se Chung Oh ,  Sung Chul Lee ,  Daeeun Jeong

IPC: H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: Magnetic memory devices are provided. A magnetic memory device includes a first electrode on a substrate, a magnetic tunnel junction pattern including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer, which are sequentially stacked on the first electrode, and a second electrode on the magnetic tunnel junction pattern. A surface binding energy of the first electrode and/or the second electrode with respect to the magnetic tunnel junction pattern is relatively low.

公开(公告)号：US11735241B2

公开(公告)日：2023-08-22

申请号：US17202648

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Ju Shin ,  Sang Hwan Park ,  Se Chung Oh ,  Ki Woong Kim ,  Hyeon Woo Seo

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 Å to 2.0 Å. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 Å to 5.0 Å. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.

公开(公告)号：US11706931B2

公开(公告)日：2023-07-18

申请号：US17230029

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Kim ,  Sang Hwan Park ,  Yong-Sung Park ,  Hyeonwoo Seo ,  Se Chung Oh ,  Hyun Cho

IPC: H10B61/00 ,  H10B63/00

CPC classification number: H10B61/22 ,  H10B63/34 ,  H10B63/845

Abstract: A variable resistance memory device including a substrate; horizontal structures spaced apart from each other in a first direction perpendicular to a top surface of the substrate; variable resistance patterns on the horizontal structures, respectively; and conductive lines on the variable resistance patterns, respectively, wherein each of the horizontal structures includes a first electrode pattern, a semiconductor pattern, and a second electrode pattern arranged along a second direction parallel to the top surface of the substrate, and each of the variable resistance patterns is between one of the second electrode patterns and a corresponding one of the conductive lines.

公开(公告)号：US11725271B2

公开(公告)日：2023-08-15

申请号：US17721428

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  H01J37/32 ,  C23C14/08 ,  H01J37/34

CPC classification number: C23C14/3464 ,  C23C14/08 ,  C23C14/352 ,  H01J37/32082 ,  H01J37/32155 ,  H01J37/32715 ,  H01J37/3417

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

公开(公告)号：US20210010127A1

公开(公告)日：2021-01-14

申请号：US16793096

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  C23C14/08 ,  H01J37/32

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

公开(公告)号：US20250017118A1

公开(公告)日：2025-01-09

申请号：US18412778

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Chung Oh ,  JeongMok Kim ,  Tanyoung Kim ,  Heeju Shin ,  YoungJun Cho

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20

Abstract: A magnetic memory device includes a reference magnetic pattern and a free magnetic pattern stacked on a substrate, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a first non-magnetic pattern on the free magnetic pattern, the free magnetic pattern being between the tunnel barrier pattern and the first non-magnetic pattern, a second non-magnetic pattern on the first non-magnetic pattern, the first non-magnetic pattern being between the free magnetic pattern and the second non-magnetic pattern, a metal pattern between the first non-magnetic pattern and the second non-magnetic pattern, and a conductive layer on a side surface of the first non-magnetic pattern.

公开(公告)号：US11683992B2

公开(公告)日：2023-06-20

申请号：US17134456

申请日：2020-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjong Jeong ,  Ki Woong Kim ,  Younghyun Kim ,  Junghwan Park ,  Byoungjae Bae ,  Se Chung Oh ,  Jungmin Lee ,  Kyungil Hong

IPC: H10N50/80 ,  H10N50/01 ,  H10B61/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.

公开(公告)号：US11600662B2

公开(公告)日：2023-03-07

申请号：US17582628

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwan Park ,  Younghyun Kim ,  Se Chung Oh ,  Jungmin Lee ,  Kyungil Hong

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  H01L43/04 ,  H01L43/06

Abstract: Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

公开(公告)号：US11339467B2

公开(公告)日：2022-05-24

申请号：US16793096

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  H01J37/32 ,  C23C14/08

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.