公开(公告)号：US20240279835A1

公开(公告)日：2024-08-22

申请号：US18654247

申请日：2024-05-03

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: C25D3/38 ,  C22C9/04 ,  C25D5/02 ,  C25D5/10 ,  C25D5/50 ,  C25D7/12 ,  H01L23/00

CPC classification number: C25D3/38 ,  C25D5/022 ,  C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  C22C9/04 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/13026 ,  H01L2224/13082

Abstract: A microelectronic device is formed by forming a seed layer that contains primarily zinc. A plating mask is formed over the seed layer, and a copper strike layer is formed on the seed layer using a neutral pH copper plating bath. A main copper layer is formed on the copper strike layer by plating copper on the copper strike layer. The plating mask is subsequently removed. The main copper layer, the copper strike layer, and the seed layer are heated to diffuse copper and zinc, and form a brass layer under the main copper layer, consuming the seed layer between the main copper layer and the substrate. Remaining portions of the seed layer are removed by a wet etch process. The main copper layer and the underlying brass layer provide a conductor structure.

公开(公告)号：US20240153853A1

公开(公告)日：2024-05-09

申请号：US18389651

申请日：2023-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/15747 ,  H01L2924/35121

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US20230298982A1

公开(公告)日：2023-09-21

申请号：US17720159

申请日：2022-04-13

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49582 ,  H01L21/4821 ,  H01L23/49534 ,  H01L23/49548 ,  H01L24/48

Abstract: An electronic device includes a semiconductor die, a package structure enclosing the semiconductor die, and a conductive lead having first and second surfaces. The first surface has a bilayer exposed along a bottom side of the package structure, and the second surface is exposed along another side of the package structure. The bilayer includes first and second plated layers, the first plated layer on and contacting the first surface of the conductive lead and the second plated layer on and contacting the first plated layer and exposed along the bottom side of the package structure, where the first plated layer includes cobalt, and the second plated layer includes tin.

公开(公告)号：US20230243770A1

公开(公告)日：2023-08-03

申请号：US18180572

申请日：2023-03-08

Applicant: Texas Instruments Incorporated

Inventor： Archana VENUGOPAL ,  Benjamin Stassen Cook ,  Nazila Dadvand ,  Luigi Colombo

IPC: G01N27/12 ,  G01N33/00 ,  H01L29/06 ,  H01L29/16 ,  C23C16/04 ,  C23C18/06 ,  C23C18/16 ,  C23C16/26 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: G01N27/127 ,  G01N33/0027 ,  G01N27/128 ,  H01L29/0669 ,  H01L29/1606 ,  C23C16/042 ,  C23C16/04 ,  C23C18/06 ,  C23C18/1605 ,  C23C18/1603 ,  C23C16/047 ,  C23C18/1607 ,  C23C18/1657 ,  C23C16/26 ,  C23C18/1648 ,  B33Y10/00 ,  B33Y80/00 ,  H01L21/02606

Abstract: A gas sensor has a microstructure sensing element which comprises a plurality of interconnected units wherein the units are formed of connected graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US11410947B2

公开(公告)日：2022-08-09

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

公开(公告)号：US11370662B2

公开(公告)日：2022-06-28

申请号：US16230070

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: C01B21/064 ,  C23C16/34 ,  C23C18/32 ,  C23C18/16 ,  C23C18/36 ,  C23C18/28 ,  C23C18/30 ,  C23C18/20 ,  G03F1/60 ,  G03F1/20 ,  C23C18/38 ,  C23C18/42

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

公开(公告)号：US20210375729A1

公开(公告)日：2021-12-02

申请号：US17404946

申请日：2021-08-17

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri ,  Nazila Dadvand

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  C25D7/00 ,  H01L23/31

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

公开(公告)号：US20200303285A1

公开(公告)日：2020-09-24

申请号：US16359628

申请日：2019-03-20

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/14 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  C25D7/12 ,  C25D3/38

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

公开(公告)号：US20200286844A1

公开(公告)日：2020-09-10

申请号：US16292975

申请日：2019-03-05

Applicant: Texas Instruments Incorporated

Inventor： Keith Edward Johnson ,  Nazila Dadvand

IPC: H01L23/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/24

Abstract: In a described example, a method is described including: depositing a zinc seed layer on a substrate; forming a photoresist pattern on the zinc seed layer, with openings in the photoresist pattern exposing portions of the zinc seed layer; electroplating a copper structure onto the exposed portions of the zinc seed layer; stripping the photoresist; annealing the substrate to form copper/zinc alloy between the copper structure and the substrate; and etching away the unreacted portions of the zinc seed layer.

公开(公告)号：US20200161210A1

公开(公告)日：2020-05-21

申请号：US16193089

申请日：2018-11-16

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/373 ,  H01L21/288 ,  H01L21/285 ,  H01L21/78 ,  H01L21/768 ,  C23C14/16 ,  C23C18/38 ,  C25D3/46 ,  C25D3/38

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.