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公开(公告)号：US12087395B2
公开(公告)日：2024-09-10
申请号：US17558847
申请日：2021-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Steven Craig Bartling , Sudhanshu Khanna
IPC: G06F1/00 , G06F1/3203 , G06F1/3234 , G06F1/3287 , G06F3/06 , G06F9/4401 , G06F11/10 , G06F11/14 , G06F12/02 , G06F13/00 , G11C7/22 , G11C14/00 , H03K3/3562
CPC classification number: G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/00 , Y02D30/50
Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.
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2.发明授权公开(公告)号：US11953969B2
公开(公告)日：2024-04-09
申请号：US17404125
申请日：2021-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Zwerg , Steven Craig Bartling , Sudhanshu Khanna
IPC: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/06 , G06F11/07
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0655 , G06F3/0656 , G06F3/0688 , G06F11/07 , Y02D10/00 , Y02D30/50
Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.
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公开(公告)号：US11847430B2
公开(公告)日：2023-12-19
申请号：US17521019
申请日：2021-11-08
Applicant: Texas Instruments Incorporated
Inventor： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
CPC classification number: G06F7/62 , G06F1/26 , G06F1/30 , G08C13/02 , H03K5/24 , G11C11/56 , H03K21/40 , H03K21/403
Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.
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公开(公告)号：US20220057996A1
公开(公告)日：2022-02-24
申请号：US17521019
申请日：2021-11-08
Applicant: Texas Instruments Incorporated
Inventor： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.
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公开(公告)号：US11243903B2
公开(公告)日：2022-02-08
申请号：US16658928
申请日：2019-10-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10037071B2
公开(公告)日：2018-07-31
申请号：US14918133
申请日：2015-10-20
Applicant: Texas Instruments Incorporated
Inventor： Andreas Dannenberg , Brent Peterson , Aik K. Goh , Joerg Schreiner , Michael Zwerg , Steven Craig Bartling
IPC: G06F1/00 , G06F1/32 , G06F12/02 , G06F9/4401
CPC classification number: G06F1/3275 , G06F1/3243 , G06F1/3287 , G06F9/4418 , G06F12/0246 , G06F2212/7203 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/44 , Y02D50/20
Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.
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公开(公告)号：US20170109054A1
公开(公告)日：2017-04-20
申请号：US14887885
申请日：2015-10-20
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G06F13/4234 , G06F13/28 , H04L67/303
Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.
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公开(公告)号：US09454437B2
公开(公告)日：2016-09-27
申请号：US14309362
申请日：2014-06-19
Inventor： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。
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公开(公告)号：US09335954B2
公开(公告)日：2016-05-10
申请号：US13770448
申请日：2013-02-19
Applicant: Texas Instruments Incorporated
Inventor： Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/17 , Y02D10/171 , Y02D50/20
Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.
Abstract translation: 处理设备的设计和操作可配置为在非易失性存储器恢复机器状态期间优化唤醒时间和峰值功耗成本。 处理装置包括被配置为存储由处理装置的多个易失性存储元件表示的机器状态的多个非易失性逻辑元件阵列。 将存储的机器状态从多个非易失性逻辑元件阵列读出到多个易失性存储元件。 在制造期间，非易失性逻辑元件阵列中每行的数行和数位数是基于目标唤醒时间和峰值功率成本的。 在另一种方法中，可以并行，顺序地或以任何组合来对数据进行数据写入或读取数据，以优化操作特性。
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公开(公告)号：US09013218B2
公开(公告)日：2015-04-21
申请号：US14311831
申请日：2014-06-23
Applicant: Texas Instruments Incorporated
Inventor： Steven Craig Bartling , Sudhanshu Khanna
CPC classification number: H03K3/0375 , H03K3/356008
Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.
Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。 信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。
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