公开(公告)号：US12217936B2

公开(公告)日：2025-02-04

申请号：US18504415

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01L21/02 ,  H01J37/32 ,  H01L21/311 ,  H01L21/321

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US20240413020A1

公开(公告)日：2024-12-12

申请号：US18488393

申请日：2023-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chun-I Tsai ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo ,  Wei-Jung Lin ,  Yu-Ting Wen ,  Kai-Chieh Yang

IPC: H01L21/8238 ,  H01L21/321 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

公开(公告)号：US12159837B2

公开(公告)日：2024-12-03

申请号：US18094866

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US11854766B2

公开(公告)日：2023-12-26

申请号：US17869557

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC: H01L21/321 ,  H01L21/311 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01J37/32027 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/0212 ,  H01L21/02063 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31138 ,  H01L21/321 ,  H01J2237/3341

Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US11552018B2

公开(公告)日：2023-01-10

申请号：US17306784

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

公开(公告)号：US11245033B2

公开(公告)日：2022-02-08

申请号：US16049358

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Carlos H. Diaz ,  Chun-Hsiung Lin ,  Huicheng Chang ,  Syun-Ming Jang ,  Chien-Hsun Wang ,  Mao-Lin Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

公开(公告)号：US20200020784A1

公开(公告)日：2020-01-16

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

公开(公告)号：US20160172466A1

公开(公告)日：2016-06-16

申请号：US15043759

申请日：2016-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66537 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66651

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract translation: 本公开涉及一种形成晶体管器件的方法。 在该方法中，第一和第二阱区形成在半导体衬底内。 第一和第二阱区域分别具有彼此不同的第一和第二蚀刻速率。 将掺杂剂选择性地注入第一阱区以改变第一蚀刻速率以使第一蚀刻速率基本上等于第二蚀刻速率。 蚀刻第一选择性注入的阱区和第二阱区以形成具有相等凹槽深度的沟槽。 进行外延生长工艺以在通道凹槽内形成一个或多个外延层。

公开(公告)号：US20140264866A1

公开(公告)日：2014-09-18

申请号：US13832195

申请日：2013-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jiun Liu ,  Chen-Yuan Kao ,  Hung-Wen Su ,  Mingh-Hsing Tsai ,  Syun-Ming Jang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract translation: 描述了具有改进的金属结构的半导体结构。 半导体结构可以包括具有上表面的衬底，在上表面上的互连层，以及沉积在互连层上的附加结构。 互连层可以包括衬底上的图案化种子层，种子层上的至少两条金属线以及相邻金属线之间的电介质材料。 阻挡层可沉积在至少两条金属线上。 还描述了制造半导体结构的方法。

公开(公告)号：US20240355740A1

公开(公告)日：2024-10-24

申请号：US18345303

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Yu Chang ,  Sheng-Hsuan Lin ,  Shu-Lan Chang ,  Kai-Yi Chu ,  Meng-Hsien Lin ,  Pei-Hsuan Lee ,  Pei Shan Chang ,  Chih-Chien Chi ,  Chun-I Tsai ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/53266 ,  H01L21/7684 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.