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    Semiconductor memory having stacked capacitor
    2.
    发明授权
    Semiconductor memory having stacked capacitor 失效
    半导体存储器具有层叠电容

    公开(公告)号：US5012310A

    公开(公告)日：1991-04-30

    申请号：US566315

    申请日：1990-08-13

    申请人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    发明人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10808

    摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

    摘要翻译： 公开了一种实现高集成度和高​​可靠性的兆比特动态随机存取存储器。 消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。 每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

    Method for formation of insulation film on silicon buried in trench
    3.
    发明授权
    Method for formation of insulation film on silicon buried in trench 失效
    在埋在沟槽中的硅上形成绝缘膜的方法

    公开(公告)号：US4873203A

    公开(公告)日：1989-10-10

    申请号：US221351

    申请日：1988-07-19

    申请人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    发明人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    IPC分类号： H01L27/04 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L29/66181 ,  H01L21/32 ,  H01L21/763

    摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.

    摘要翻译： 通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜 第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。 埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。 在将来将形成有源元件的部分处的基板的表面不被氧化。

    Semiconductor memory having trench capacitor formed with sheath electrode
    5.
    发明授权
    Semiconductor memory having trench capacitor formed with sheath electrode 失效
    具有形成有护套电极的沟槽电容器的半导体存储器

    公开(公告)号：US4918502A

    公开(公告)日：1990-04-17

    申请号：US123235

    申请日：1987-11-20

    申请人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

    发明人： Toru Kaga ,  Shinichiro Kimura ,  Hideo Sunami

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10829

    摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.

    摘要翻译： 本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。 本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分 电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。 此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。

    Dynamic random access memory having buried word lines
    6.
    发明授权
    Dynamic random access memory having buried word lines 失效
    具有掩埋字线的动态随机存取存储器

    公开(公告)号：US4873560A

    公开(公告)日：1989-10-10

    申请号：US155698

    申请日：1988-02-16

    申请人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

    发明人： Hideo Sunami ,  Shinichiro Kimura ,  Toru Kaga

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10841 ,  Y10S257/922

    摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.

    摘要翻译： 本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。 在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成 开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。

    Method of fabricating stacked capacitor cell memory devices
    7.
    发明授权
    Method of fabricating stacked capacitor cell memory devices 失效
    叠层电容器单元存储器件的制造方法

    公开(公告)号：US5374576A

    公开(公告)日：1994-12-20

    申请号：US72482

    申请日：1993-06-03

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06878586B2

    公开(公告)日：2005-04-12

    申请号：US10458271

    申请日：2003-06-11

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/8242

    CPC分类号： H01L27/10817 ,  H01L27/10808 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。