公开(公告)号：US10431497B1

公开(公告)日：2019-10-01

申请号：US15951192

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/321 ,  H01L21/28

Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

公开(公告)号：US20160093616A1

公开(公告)日：2016-03-31

申请号：US14526552

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US20190221639A1

公开(公告)日：2019-07-18

申请号：US15870267

申请日：2018-01-12

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.

公开(公告)号：US10211313B2

公开(公告)日：2019-02-19

申请号：US15678125

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

公开(公告)号：US10707135B2

公开(公告)日：2020-07-07

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/167 ,  H01L21/762 ,  H01L21/266 ,  H01L21/265

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.

公开(公告)号：US20190295896A1

公开(公告)日：2019-09-26

申请号：US15951192

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L21/321

Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

公开(公告)号：US20190131183A1

公开(公告)日：2019-05-02

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.

公开(公告)号：US09685383B2

公开(公告)日：2017-06-20

申请号：US14711752

申请日：2015-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Hsien Yeh ,  Zhen Wu ,  Yen-Cheng Chang ,  Yu-Ting Tseng

IPC: H01L21/321 ,  H01L21/283 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/823821 ,  H01L21/02041 ,  H01L21/28088 ,  H01L21/31133 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20190140068A1

公开(公告)日：2019-05-09

申请号：US16239541

申请日：2019-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40

Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.