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    METHOD OF FORMING FET SILICIDE GATE STRUCTURES INCORPORATING INNER SPACERS
    1.
    发明申请
    METHOD OF FORMING FET SILICIDE GATE STRUCTURES INCORPORATING INNER SPACERS 失效
    形成内置空间的FET硅胶结构的方法

    公开(公告)号：US20050153494A1

    公开(公告)日：2005-07-14

    申请号：US10707759

    申请日：2004-01-09

    申请人： Victor Ku ,  An Steegen ,  Hsing-Jen Wann ,  Keith Wong

    发明人： Victor Ku ,  An Steegen ,  Hsing-Jen Wann ,  Keith Wong

    IPC分类号： H01L21/335 ,  H01L21/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    摘要： A method is provided for fabricating a gate structure for a semiconductor device in which the gate structure has an inner spacer. A replacement-gate process is used in which material is removed in a gate region to expose a portion of the substrate; a gate dielectric is formed on the exposed portion of the substrate; and an inner spacer layer is formed overlying the gate dielectric and the dielectric material. A silicon layer is then formed which overlies the inner spacer layer. The structure is then planarized so that portions of the silicon layer and inner spacer layer remain in the gate region. A silicide gate structure is then formed from the silicon; the silicide gate structure is separated from dielectric material surrounding the gate by the inner spacer layer. The semiconductor device may include a first gate region and a second gate region with an interface therebetween, with the inner spacer layer covering the interface. When the device has two gate regions, the process may be used in both gate regions, so as to produce separate silicide structures, with an inner spacer separating the two structures.

    摘要翻译： 提供了一种用于制造半导体器件的栅极结构的方法，其中栅极结构具有内部间隔物。 使用替代栅极工艺，其中在栅极区域中去除材料以暴露基板的一部分; 栅极电介质形成在衬底的暴露部分上; 并且形成覆盖栅极电介质和电介质材料的内部间隔层。 然后形成覆盖在内间隔层上的硅层。 然后将该结构平坦化，使得硅层和内部间隔层的部分保留在栅极区域中。 然后从硅形成硅化物栅极结构; 硅化物栅极结构通过内部间隔层与围绕栅极的介电材料分离。 半导体器件可以包括第一栅极区域和其间具有界面的第二栅极区域，内部间隔层覆盖界面。 当器件具有两个栅极区域时，该工艺可以在两个栅极区域中使用，以便产生分离的硅化物结构，其中分隔两个结构的内部间隔物。

    Introduction of metal impurity to change workfunction of conductive electrodes
    2.
    发明申请
    Introduction of metal impurity to change workfunction of conductive electrodes 有权
    引入金属杂质来改变导电电极的功能

    公开(公告)号：US20070173008A1

    公开(公告)日：2007-07-26

    申请号：US11336727

    申请日：2006-01-20

    申请人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    发明人： Michael Chudzik ,  Bruce Doris ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Yun Wang ,  Keith Wong

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.

    摘要翻译： 提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数 材料层与导电电极一起存在于电极堆叠中。 金属杂质的选择取决于电极是否具有n型功函数或p型功函数。 本发明还提供一种制造这种半导体结构的方法。 金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成 包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

    Precharging scheme for reading a memory cell
    5.
    发明授权
    Precharging scheme for reading a memory cell 有权
    读取存储单元的预充电方案

    公开(公告)号：US06771543B2

    公开(公告)日：2004-08-03

    申请号：US10226912

    申请日：2002-08-22

    申请人： Keith Wong ,  Pau-Ling Chen ,  Michael S. Chung

    发明人： Keith Wong ,  Pau-Ling Chen ,  Michael S. Chung

    IPC分类号： G11C1606

    CPC分类号： G11C16/26 ,  G11C7/12 ,  G11C16/0491

    摘要： A method of reading a memory cell, and a memory array using the method, are described. An electrical load is applied to a first node in the memory array, the first node corresponding to the memory cell. A second node in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.

    摘要翻译： 描述读取存储单元的方法和使用该方法的存储器阵列。 将电负载施加到存储器阵列中的第一节点，第一节点对应于存储器单元。 存储器阵列中的第二个节点，与第一个节点相同的字线上的第二个节点被预充电。 第二节点与同一字线中的至少一个中间节点与第一节点分离。

    Label-Free Optical Sensing and Characterization of Biomolecules by D8 or D10 Metal Complexes
    6.
    发明申请
    Label-Free Optical Sensing and Characterization of Biomolecules by D8 or D10 Metal Complexes 有权
    D8或D10金属络合物的无标记光学感应和生物分子表征

    公开(公告)号：US20070190549A1

    公开(公告)日：2007-08-16

    申请号：US11625109

    申请日：2007-01-19

    申请人： Vivian Yam ,  Cong Yu ,  Kenneth Chan ,  Keith Wong

    发明人： Vivian Yam ,  Cong Yu ,  Kenneth Chan ,  Keith Wong

    IPC分类号： G01N33/53 ,  C12Q1/68

    CPC分类号： C12Q1/68 ,  C07D239/47 ,  C07D401/14 ,  C07D487/04 ,  C07F15/0086 ,  G01N33/52 ,  C12Q2565/113 ,  C12Q2563/137

    摘要： The present invention provides a composition for detecting and/or characterizing a multiple-charged biomolecule comprising a charged d8 or d10 metal complex, wherein the metal complex electrostatically binds to the multiple-charged biomolecule to induce aggregation and self-assembly of the metal complex through metal . . . metal interactions, π . . . π interactions, or a combination of both interactions. The present invention further provides assay methods and kits for label-free optical detection and/or characterization of biomolecules carrying multiple charges, e.g., single-stranded nucleic acids, polyaspartate, polyglutamate, using a composition comprising a charged d8 or d10 metal complex.

    摘要翻译： 本发明提供了一种用于检测和/或表征包含带电d 8或d 10金属络合物的多电荷生物分子的组合物，其中金属络合物静电结合到 多电荷生物分子通过金属诱导金属络合物的聚集和自组装。 。 。 金属相互作用 。 。 pi相互作用或两种相互作用的组合。 本发明进一步提供了用于无携带光学检测和/或表征携带多种电荷的生物分子的测定方法和试剂盒，例如单链核酸，聚天冬氨酸，聚谷氨酸，使用包含带电荷的d SUP>或d 10金属络合物。

    Conductor-dielectric structure and method for fabricating
    7.
    发明申请
    Conductor-dielectric structure and method for fabricating 审中-公开
    导体 - 电介质结构及其制造方法

    公开(公告)号：US20070117377A1

    公开(公告)日：2007-05-24

    申请号：US11286093

    申请日：2005-11-23

    申请人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Wong

    发明人： Chih-Chao Yang ,  Shom Ponoth ,  David Rath ,  Keith Wong

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089

    摘要： A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

    摘要翻译： 通过提供包括其中具有图案化特征的电介质层的结构来制造导体 - 电介质互连结构; 在所述图案化特征中的所述电介质层上沉积电镀种子层; 在通孔的电镀种子层上沉积牺牲种子层; 通过反向电镀减少牺牲种子层的厚度; 以及在所述图案化特征中的所述牺牲种子层上镀覆导电金属。 还提供了其中具有通孔的电介质层; 图案化特征中的电介质层上的电镀种子层; 以及位于图案化特征中的不连续牺牲种子层。

    METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION
    8.
    发明申请
    METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION 有权
    用于控制硅化物形成中的阻塞和桥接的方法

    公开(公告)号：US20050255699A1

    公开(公告)日：2005-11-17

    申请号：US10709534

    申请日：2004-05-12

    申请人： Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    发明人： Bradley Jones ,  Christian Lavoie ,  Robert Purtell ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/78

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/7833

    摘要： A method for forming a metal suicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

    摘要翻译： 用于形成用于半导体器件的金属硅化物接触的方法包括在包括所述衬底的有源和非有源区域的衬底上形成难熔金属层，并在难熔金属层上形成覆盖层。 反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力 层和盖层。

    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
    9.
    发明授权
    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed 有权
    在半导体结构中的金属硅化物层的顶部上形成TiN层的方法和形成的结构

    公开(公告)号：US06436823B1

    公开(公告)日：2002-08-20

    申请号：US09679738

    申请日：2000-10-05

    申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

    IPC分类号： H01L2144

    CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

    摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

    摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。