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    CHIP SCALE SENSING CHIP PACKAGE
    1.
    发明申请
    CHIP SCALE SENSING CHIP PACKAGE 有权

    公开(公告)号：US20170213865A1

    公开(公告)日：2017-07-27

    申请号：US15410715

    申请日：2017-01-19

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Chi-Chang LIAO ,  Shih-Yi LEE ,  Yen-Kang RAW

    IPC: H01L27/146

    CPC classification number: H01L27/14621 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L2224/11

    Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
    芯片包装及其制造方法

    公开(公告)号：US20160322305A1

    公开(公告)日：2016-11-03

    申请号：US15139276

    申请日：2016-04-26

    Applicant: XINTEC INC.

    Inventor： Shih-Yi LEE ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

    IPC: H01L23/538 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

    Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

    Abstract translation: 芯片封装包括芯片，激光停止层，第一通孔，隔离层，第二通孔和导电层。 激光停止层设置在芯片的第一表面之上，并且第一通孔从芯片的第二表面延伸到第一表面以暴露激光停止层。 隔离层位于第二表面下方，在第一通孔中，隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第一表面，第二通孔穿过第一通孔以暴露激光停止层。 导电层设置在第三表面下方并延伸到第二通孔中以接触激光停止层。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    5.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160204061A1

    公开(公告)日：2016-07-14

    申请号：US14992776

    申请日：2016-01-11

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

    IPC: H01L23/522 ,  H01L21/304 ,  H01L21/268 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  G06K9/0002 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5283 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

    Abstract translation: 一种芯片封装，包括芯片，第一通孔，导电结构，第一隔离层，第二通孔和第一导电层。 第一通孔从第二表面延伸到第一表面以暴露导电焊盘，并且导电结构在第二表面上并延伸到第一通孔以接触导电焊盘。 导电结构包括第二导电层和激光器塞。 第一隔离层位于第二表面上并覆盖导电结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光阻挡件，并且第一导电层在第三表面上并延伸到第二通孔以接触激光器塞。

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