公开(公告)号：US20110254150A1

公开(公告)日：2011-10-20

申请号：US13114554

申请日：2011-05-24

申请人： Yoshimi Takahashi ,  Masazumi Amagai

发明人： Yoshimi Takahashi ,  Masazumi Amagai

IPC分类号： H01L23/52

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件允许单独模制承载在衬底表面上的多个半导体芯片。 它包括以下工艺步骤：在衬底100的表面上布置多个半导体元件102的工艺步骤; 其中衬底102的内侧固定在下模130上的工艺步骤; 其中液体树脂114从喷嘴112供应到每个半导体元件上以覆盖每个半导体芯片102的至少一部分的工艺步骤; 将具有形成在一个表面上的多个空腔144的上模压在下模上的处理步骤，并且液态树脂114通过多个空腔144在规定温度下成型; 以及上模140的空腔144与基板分离的工序，单独形成多个成形树脂部。

公开(公告)号：US07971351B2

公开(公告)日：2011-07-05

申请号：US12400474

申请日：2009-03-09

申请人： Yoshimi Takahashi ,  Masazumi Amagai

发明人： Yoshimi Takahashi ,  Masazumi Amagai

IPC分类号： H05K3/30

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件允许单独模制承载在衬底表面上的多个半导体芯片。 它包括以下工艺步骤：在衬底100的表面上布置多个半导体元件102的工艺步骤; 其中衬底102的内侧固定在下模130上的工艺步骤; 其中液体树脂114从喷嘴112供应到每个半导体元件上以覆盖每个半导体芯片102的至少一部分的工艺步骤; 将具有形成在一个表面上的多个空腔144的上模压在下模上的处理步骤，并且液态树脂114通过多个空腔144在规定温度下成型; 以及上模140的空腔144与基板分离的工序，单独形成多个成形树脂部。

公开(公告)号：US08304883B2

公开(公告)日：2012-11-06

申请号：US13114554

申请日：2011-05-24

申请人： Yoshimi Takahashi ,  Masazumi Amagai

发明人： Yoshimi Takahashi ,  Masazumi Amagai

IPC分类号： H01L23/22 ,  H01L21/00 ,  H05K3/30

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件允许单独模制承载在衬底表面上的多个半导体芯片。 它包括以下工艺步骤：在衬底100的表面上布置多个半导体元件102的工艺步骤; 其中衬底102的内侧固定在下模130上的工艺步骤; 其中液体树脂114从喷嘴112供应到每个半导体元件上以覆盖每个半导体芯片102的至少一部分的工艺步骤; 将具有形成在一个表面上的多个空腔144的上模压在下模上的处理步骤，并且液态树脂114通过多个空腔144在规定温度下成型; 以及上模140的空腔144与基板分离的工序，单独形成多个成形树脂部。

公开(公告)号：US07520052B2

公开(公告)日：2009-04-21

申请号：US11426622

申请日：2006-06-27

申请人： Yoshimi Takahashi ,  Masazumi Amagai

发明人： Yoshimi Takahashi ,  Masazumi Amagai

IPC分类号： H05K3/30

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件允许单独模制承载在衬底表面上的多个半导体芯片。 它包括以下工艺步骤：在衬底100的表面上布置多个半导体元件102的工艺步骤; 其中衬底102的内侧固定在下模130上的工艺步骤; 其中液体树脂114从喷嘴112供应到每个半导体元件上以覆盖每个半导体芯片102的至少一部分的工艺步骤; 将具有形成在一个表面上的多个空腔144的上模压在下模上的处理步骤，并且液态树脂114通过多个空腔144在规定温度下成型; 以及上模140的空腔144与基板分离的工序，单独形成多个成形树脂部。

公开(公告)号：US20060292753A1

公开(公告)日：2006-12-28

申请号：US11426622

申请日：2006-06-27

申请人： Yoshimi Takahashi ,  Masazumi Amagai

发明人： Yoshimi Takahashi ,  Masazumi Amagai

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L21/67126 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements 102 are arranged on the surface of substrate 100; a process step in which the inner side of substrate 102 is fixed on lower die 130; a process step in which liquid resin 114 is supplied from nozzle 112 onto each of the semiconductor elements in order to cover at least a portion of each of semiconductor chips 102; a process step in which the upper die having plural cavities 144 formed in one surface is pressed onto the lower die, and liquid resin 114 is molded at a prescribed temperature by means of plural cavities 144; and a process step in which cavities 144 of upper die 140 are detached from the substrate, and plural molding resin portions are formed individually.

摘要翻译： 本发明的目的是提供一种制造半导体器件的方法，该半导体器件允许单独模制承载在衬底表面上的多个半导体芯片。 它包括以下工艺步骤：在衬底100的表面上布置多个半导体元件102的工艺步骤; 其中衬底102的内侧固定在下模130上的工艺步骤; 其中液体树脂114从喷嘴112供应到每个半导体元件上以覆盖每个半导体芯片102的至少一部分的工艺步骤; 将具有形成在一个表面上的多个空腔144的上模压在下模上的处理步骤，并且液态树脂114通过多个空腔144在规定温度下成型; 以及上模140的空腔144与基板分离的工序，单独形成多个成形树脂部。

公开(公告)号：US20120220080A1

公开(公告)日：2012-08-30

申请号：US13466449

申请日：2012-05-08

申请人： Masako Watanabe ,  Masazumi Amagai

发明人： Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L21/78

CPC分类号： A61B17/1757 ,  A61B17/1671 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/27438 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012

摘要： A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached.

摘要翻译： 一种半导体器件，其包括具有轮廓的工件和多个接触焊盘，并且还包括具有多个端子焊盘的外部部件。 该部分与工件间隔开，并且端子焊盘分别与工件接触焊盘对准。 回流元件将每个接触焊盘与其相应的端子焊盘互连。 热塑性材料填充工件与零件之间的空间; 该材料粘附到工件，部件和回流元件上。 此外，该材料具有与工件的轮廓基本一致的轮廓，并且基本上没有空隙填充空间。 由于填充材料的热塑性特征，当达到回流元件的温度范围时，可以对成品装置进行再加工。

公开(公告)号：US07679002B2

公开(公告)日：2010-03-16

申请号：US11466219

申请日：2006-08-22

申请人： Masazumi Amagai ,  Kenji Masumoto

发明人： Masazumi Amagai ,  Kenji Masumoto

IPC分类号： H05K1/16

CPC分类号： H01L23/3128 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

摘要翻译： 一方面，本发明提供一种包括半导体器件封装衬底芯的半导体器件。 第一互连结构位于模具区域内并且在衬底芯的裸片侧上并且具有与其相关联的第一导电金属密度。 第二互连结构位于模具区域内并且位于衬底芯的焊接侧上并且具有与其相关联的第二导电金属密度，其中模具区域内的第二导电金属密度约等于或小于第一导电 模具区域内的金属密度。

公开(公告)号：US20100025837A1

公开(公告)日：2010-02-04

申请号：US12446827

申请日：2007-10-22

申请人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

发明人： Tomonori Shinoda ,  Hironori Shizuhata ,  Hirofumi Shinoda ,  Yuji Kawamata ,  Takeshi Tashima ,  Masato Shimamura ,  Masako Watanabe ,  Masazumi Amagai

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L21/70

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: an upper semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on a lower surface in the upper semiconductor package and a principal part of the upper semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively upper part, a lower semiconductor package which comprises a substrate for wiring and connecting provided with electrodes for conducting packages on an upper surface in the lower semiconductor package and a principal part of the lower semiconductor package disposed on an upper surface and/or a lower surface of the above substrate and which constitutes a relatively lower part, a spacer sheet which comprises a space part corresponding to the principal part of the upper semiconductor package and/or the principal part of the lower semiconductor package disposed between the adjacent upper and lower substrates and through holes disposed in a periphery of the above space part and allowing the electrodes oppositely disposed between the substrates to be communicated with each other and which is adhered onto the above substrates and inserted therebetween, connection terminals which are provided in an inside of the through holes in the spacer sheet and which are used for conducting the substrates and connection terminals for external connection which are formed on a lower surface of a substrate for wiring and connecting in a semiconductor package located in a lowermost part and to a production process for the same. The present invention provides a wiring and connecting method by a spacer sheet which ensures an installation space between an upper semiconductor package and a lower semiconductor package in a POP type semiconductor package and prevents short circuit between adjacent connection terminals and which can certainly wire and connect both semiconductor packages, and a complex type semiconductor device of a POP type having a high packaging density prepared is provided by the above method.

公开(公告)号：US07029542B2

公开(公告)日：2006-04-18

申请号：US10614351

申请日：2003-07-08

申请人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Osamu Munekata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Hiroshi Okada

发明人： Masazumi Amagai ,  Masako Watanabe ,  Kensho Murata ,  Osamu Munekata ,  Yoshitaka Toyoda ,  Minoru Ueshima ,  Tsukasa Ohnishi ,  Hiroshi Okada

IPC分类号： C22C13/00 ,  B23K35/26

CPC分类号： B23K35/262 ,  B23K35/0244 ,  B23K2101/42

摘要： A lead-free solder alloy comprises 1.0–5.0 wt % Ag, 0.01–0.5 wt % Ni, one or both of (a) 0.001–0.05 wt % Co and (b) at least one of P, Ge, and Ga in a total amount of 0.001–0.05 wt %, and a remainder of Sn. The solder can form solder bumps which have a high bonding strength and which do not undergo yellowing after soldering.

摘要翻译： 一种无铅焊料合金包含1.0-5.0重量％的Ag，0.01-0.5重量％的Ni，（a）0.001-0.05重量％的Co中的一个或两个，和（b）一个或多个P，Ge和Ga中的至少一个， 总量为0.001-0.05重量％，余量为Sn。 焊料可以形成具有高粘合强度并且在焊接后不经历黄变的焊料凸块。

公开(公告)号：US5882956A

公开(公告)日：1999-03-16

申请号：US786659

申请日：1997-01-21

申请人： Norito Umehara ,  Masazumi Amagai ,  Mamoru Kobayashi ,  Kazuyoshi Ebe

发明人： Norito Umehara ,  Masazumi Amagai ,  Mamoru Kobayashi ,  Kazuyoshi Ebe

IPC分类号： H01L21/301 ,  H01L21/304 ,  H01L21/68 ,  H01L23/495 ,  H01L21/208

CPC分类号： H01L24/83 ,  H01L21/304 ,  H01L21/6836 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/31 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181

摘要： A process for manufacturing a wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.

摘要翻译： 本发明的晶片切割/粘合片的制造方法包括软膜，形成在软膜上的压敏粘合剂层，由耐压树脂构成的聚酰亚胺树脂的加工膜，所述耐热树脂在压力 粘合剂层和形成在处理膜上的聚酰亚胺粘合剂层。 优选的是，处理膜是其表面进行醇酸树脂剥离处理的聚萘二甲酸乙二醇酯膜。 本发明便于在晶片切割之后进行扩展。