公开(公告)号：US08298874B2

公开(公告)日：2012-10-30

申请号：US13526116

申请日：2012-06-18

申请人： Bernardo Gallegos ,  Kenji Masumoto

发明人： Bernardo Gallegos ,  Kenji Masumoto

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/13 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

摘要翻译： 一种用于形成封装的电子器件的方法，其包括具有顶部衬底表面的封装衬底，所述顶部衬底表面包括其上包括至少一个焊盘焊盘的焊盘附着区域和位于焊盘焊盘侧面的第一电介质层和非裸片附着区域。 第二电介质层形成在封装衬底的顶部衬底表面上。 安装在封装基板的顶部基板表面上的IC管芯。 在IC管芯和管芯附着区域之间形成底层填充层。

公开(公告)号：US20120252170A1

公开(公告)日：2012-10-04

申请号：US13526116

申请日：2012-06-18

申请人： Bernardo Gallegos ,  Kenji Masumoto

发明人： Bernardo Gallegos ,  Kenji Masumoto

IPC分类号： H01L21/56

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/13 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

摘要翻译： 一种用于形成封装的电子器件的方法，其包括具有顶部衬底表面的封装衬底，所述顶部衬底表面包括其上包括至少一个焊盘焊盘的焊盘附着区域和位于焊盘焊盘侧面的第一电介质层和非裸片附着区域。 第二电介质层形成在封装衬底的顶部衬底表面上。 安装在封装基板的顶部基板表面上的IC管芯。 在IC管芯和管芯附着区域之间形成底层填充层。

公开(公告)号：US08115310B2

公开(公告)日：2012-02-14

申请号：US12482855

申请日：2009-06-11

申请人： Kenji Masumoto ,  Mutsumi Masumoto

发明人： Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16057 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

摘要翻译： 半导体器件组件可以包括半导体芯片，接收衬底和插入在半导体芯片和接收衬底之间的间隔结构。 间隔件在柱和粘结指之间提供了一个空余的空余物，用于过剩的导电材料，否则可能会从柱和键指之间流出，导致导电短路。 间隔件还可以提供柱和粘合指之间的偏移。

公开(公告)号：US20100289138A1

公开(公告)日：2010-11-18

申请号：US12465049

申请日：2009-05-13

申请人： Kenji Masumoto

发明人： Kenji Masumoto

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83009 ,  H01L2224/831 ,  H01L2224/83385 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

摘要： An integrated circuit (IC) and a method of forming the device are provided. The device includes a substrate and a metal trace formed on the substrate, the metal trace including a bond area and a routing area. The routing area includes a rough surface for promoting adhesion to underfill of a flip-chip die. The flip-chip die can include a bump bond connected to the bond area of the metal trace. The underfill is between the substrate and an active surface of the flip-chip die, the rough surface of the routing area adhering to the underfill in the absence of a photo resist on the routing area of the metal trace.

摘要翻译： 提供集成电路（IC）和形成该器件的方法。 该器件包括形成在衬底上的衬底和金属迹线，金属迹线包括接合区域和布线区域。 布线区域包括用于促进对倒装芯片的底部填充物的附着的粗糙表面。 倒装芯片可以包括连接到金属迹线的接合区域的凸块接合。 底部填料位于衬底和倒装芯片的有源表面之间，路由区域的粗糙表面在金属迹线的布线区域上没有光刻胶时粘附到底部填充物上。

公开(公告)号：US07157363B2

公开(公告)日：2007-01-02

申请号：US10949386

申请日：2004-09-27

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）相适应的位置处具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，该抗蚀剂膜具有在与开口部分（31a）相适应的区域中形成的开口部分，树脂突出部分（4）和夹在其间的区域。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US06992380B2

公开(公告)日：2006-01-31

申请号：US10651522

申请日：2003-08-29

申请人： Kenji Masumoto

发明人： Kenji Masumoto

IPC分类号： H01L23/043

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512

摘要： A semiconductor device 39. The device includes an interposer 31 having two major surfaces. The first surface 311 includes patterned metal conductors and bond pads 351, and the second surface includes an array of solder balls 33. The device includes a semiconductor chip 30 having a top surface and a back surface, the back surface of the chip adjacent the interposer 31, and the top surface including a plurality of terminals. Also included is a layer of polymeric material 34 disposed on the first surface 311 of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric material layer is between the chip 30 and the interposer 31. The device further includes a plurality of electrical connections 35 between the chip terminals and the bond pads 351 on the interposer.

摘要翻译： 半导体器件39。 该装置包括具有两个主表面的插入件31。 第一表面311包括图案化金属导体和接合焊盘351，并且第二表面包括焊球33的阵列。 该器件包括具有顶表面和后表面的半导体芯片30，芯片的靠近插入器31的后表面，并且顶表面包括多个端子。 还包括一层聚合材料34，其设置在插入件的第一表面311上，覆盖焊锡球阵列上的插入物的区域。 聚合材料层的至少一部分在芯片30和插入件31之间。 该装置还包括在芯片端子与插入器上的接合焊盘351之间的多个电连接35。

公开(公告)号：US06734532B2

公开(公告)日：2004-05-11

申请号：US10006576

申请日：2001-12-06

申请人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

发明人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L2358

CPC分类号： H01L23/562 ,  H01L23/3157 ,  H01L23/552 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/04941

摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output pads suitable for metallurgical contacts. Further, the device has a protective plastic film (polyimide, epoxy resin, or silicone) of controlled and uniform thickness (20 to 60 &mgr;m) selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.

摘要翻译： 一种半导体器件，包括具有有源和无源表面的半导体芯片; 主动表面包括集成电路和适用于冶金接触的输入/输出焊盘。 此外，该装置具有选择性地连接到被动表面的受控均匀厚度（20至60μm）的保护性塑料膜（聚酰亚胺，环氧树脂或硅树脂）。 该膜适于吸收可见光和紫外线波长的光，对吸湿不敏感，并在芯片上施加热机械应力，使得该应力至少部分地中和芯片组装后由外部部分施加的应力。

公开(公告)号：US20100314745A1

公开(公告)日：2010-12-16

申请号：US12482855

申请日：2009-06-11

申请人： Kenji Masumoto ,  Mutsumi Masumoto

发明人： Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16057 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

摘要翻译： 半导体器件组件可以包括半导体芯片，接收衬底和插入在半导体芯片和接收衬底之间的间隔结构。 间隔件在柱和粘结指之间提供了一个空余的空余物，用于过剩的导电材料，否则可能会从柱和键指之间流出，导致导电短路。 间隔件还可以提供柱和粘合指之间的偏移。

公开(公告)号：US20090289360A1

公开(公告)日：2009-11-26

申请号：US12470004

申请日：2009-05-21

申请人： YOSHIMI TAKAHASHI ,  KENJI MASUMOTO

发明人： YOSHIMI TAKAHASHI ,  KENJI MASUMOTO

IPC分类号： H01L23/498 ,  H01L21/60 ,  H05K1/11

CPC分类号： H05K3/3452 ,  H01L23/49811 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/167 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of forming an electronic assembly including a plurality of IC die having bonding terminals that have a solderable material thereon and a workpiece. The workpiece includes workpiece contact pads including an elevated ring having a ring height at least 5 μm above a minimum contact pad height in an indented bonding region that is within the elevated ring. The bonding terminals and/or the plurality of workpiece contact pads include solder thereon. A plurality of IC die are mounted on the workpiece. Heat is applied so that the solder becomes tacky while remaining below its melting temperature to obtain a tacked position. The plurality of IC die are pressed using a pressing tool to heat the solder to a peak temperature that is above the melting temperature. The elevated ring resists horizontal movement of the plurality of IC die from their tacked positions during pressing.

摘要翻译： 一种形成电子组件的方法，包括具有在其上具有可焊接材料的接合端子和工件的多个IC管芯。 工件包括工件接触垫，该工件接触焊盘包括在高架环内的凹陷接合区域中具有至少5mum以上的最小接触垫高度的环高度的提升环。 接合端子和/或多个工件接触焊盘在其上包括焊料。 多个IC管芯安装在工件上。 施加热量使得焊料变得发粘，同时保持低于其熔融温度以获得粘合位置。 使用加压工具对多个IC管芯进行加压，将焊料加热到高于熔融温度的峰值温度。 升高的环在压制期间抵抗多个IC芯片从其固定位置的水平移动。

公开(公告)号：US20080048303A1

公开(公告)日：2008-02-28

申请号：US11466219

申请日：2006-08-22

申请人： Masazumi Amagai ,  Kenji Masumoto

发明人： Masazumi Amagai ,  Kenji Masumoto

IPC分类号： H01L23/495

CPC分类号： H01L23/3128 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

摘要翻译： 一方面，本发明提供一种包括半导体器件封装衬底芯的半导体器件。 第一互连结构位于模具区域内并且在衬底芯的裸片侧上并且具有与其相关联的第一导电金属密度。 第二互连结构位于模具区域内并且位于衬底芯的焊接侧上并且具有与其相关联的第二导电金属密度，其中模具区域内的第二导电金属密度约等于或小于第一导电 模具区域内的金属密度。