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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC分类号： H04L41/0803 , H04L49/109 , G06F21/85
CPC分类号： H04L49/109 , G06F21/85 , H04L41/0803
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US12125533B2
公开(公告)日：2024-10-22
申请号：US17812122
申请日：2022-07-12
发明人： Francesco La Rosa , Marco Bildgen
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/26 , H10B41/35
摘要： In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.
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公开(公告)号：US12124713B2
公开(公告)日：2024-10-22
申请号：US18057390
申请日：2022-11-21
发明人： Francesco Bombaci , Andrea Tosoni
IPC分类号： G06F3/06
CPC分类号： G06F3/0629 , G06F3/0622 , G06F3/0665 , G06F3/0679
摘要： A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.
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公开(公告)号：US20240296253A1
公开(公告)日：2024-09-05
申请号：US18661060
申请日：2024-05-10
发明人： Francesco La Rosa
IPC分类号： G06F21/75 , G06F21/72 , G11C11/4096 , H01L27/088 , H03K19/17768
CPC分类号： G06F21/75 , G06F21/72 , G11C11/4096 , H01L27/0883 , H03K19/17768
摘要： An embodiment system comprises a physical unclonable function device, wherein the device comprises a first assembly of non-volatile memory cells each having a selection transistor embedded in a semiconductor substrate and a depletion-type state transistor having a control gate and a floating gate that are electrically connected, the state transistors having respective effective threshold voltages belonging to a common random distribution, and a processing circuit configured to deliver, to an output interface of the device, a group of output data based on a reading of the effective threshold voltages of the state transistors of the memory cells of the first assembly.
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公开(公告)号：US12081224B2
公开(公告)日：2024-09-03
申请号：US17807452
申请日：2022-06-17
CPC分类号： H03L7/24 , G06F1/14 , G06F9/4812 , H03L7/0992
摘要： In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
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公开(公告)号：US20240276894A1
公开(公告)日：2024-08-15
申请号：US18646334
申请日：2024-04-25
CPC分类号： H10N70/231 , H10B63/80 , H10N70/021 , H10N70/063 , H10N70/066 , H10N70/068 , H10N70/882 , H10N70/883
摘要： The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
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公开(公告)号：US12057180B2
公开(公告)日：2024-08-06
申请号：US17934102
申请日：2022-09-21
CPC分类号： G11C16/3445 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C16/349 , H10B41/30 , H10B41/40
摘要： In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
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公开(公告)号：US12051656B2
公开(公告)日：2024-07-30
申请号：US18095136
申请日：2023-01-10
发明人： Julien Delalleau , Christian Rivero
IPC分类号： H01L23/528 , H01L21/3205 , H01L21/3213 , H01L21/8234 , H01L23/00 , H01L27/02 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/45 , H01L29/49
CPC分类号： H01L23/573 , H01L21/32053 , H01L21/32133 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L29/0649 , H01L29/0847 , H01L29/1079 , H01L29/45 , H01L29/4916
摘要： An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.
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公开(公告)号：US12019510B2
公开(公告)日：2024-06-25
申请号：US17684198
申请日：2022-03-01
发明人： Albert Martinez , Patrick Haddad
摘要： The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.
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公开(公告)号：US20240194679A1
公开(公告)日：2024-06-13
申请号：US18524915
申请日：2023-11-30
IPC分类号： H01L27/092 , H01L29/40 , H01L29/417 , H01L29/78 , H02P7/03
CPC分类号： H01L27/0922 , H01L29/407 , H01L29/41741 , H01L29/41758 , H01L29/7813 , H01L29/7816 , H02P7/04
摘要： An integrated monolithic H-bridge is formed in a bulk semiconductor region. A first branch includes a first vertical MOS transistor and a second lateral MOS transistor integrated in the bulk semiconductor region. The first vertical MOS transistor and the second lateral MOS transistor are coupled in series. A second branch includes a third vertical MOS transistor and a fourth lateral MOS transistor integrated in the bulk semiconductor region. The third vertical MOS transistor and the fourth lateral MOS transistor are coupled in series and the first and second branches being coupled in parallel.
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