公开(公告)号：US12057840B1

公开(公告)日：2024-08-06

申请号：US18095436

申请日：2023-01-10

申请人： Synopsys, Inc.

发明人： Yue Yu ,  Kuan Zhou

IPC分类号： H03K3/02 ,  G11C27/02 ,  H03K3/037 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K3/037 ,  G11C27/02 ,  H03K19/1733 ,  H03K19/20

摘要： A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third size and coupled to an output of the second inverting element, and a seventh inverting element of the second size and coupled to the output of the third inverting element. The outputs of the fourth and sixth inverting elements form a first one of the differential signals. The outputs of the fifth and seventh inverting elements form a second one of the differential signals.

公开(公告)号：US11811397B1

公开(公告)日：2023-11-07

申请号：US17480026

申请日：2021-09-20

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Carl W. Werner

IPC分类号： H03K17/92 ,  H03K19/173 ,  G06F1/26 ,  H03K19/195 ,  F25D29/00

CPC分类号： H03K17/92 ,  F25D29/001 ,  G06F1/263 ,  H03K19/1733 ,  H03K19/1952

摘要： An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.

公开(公告)号：US20230258717A1

公开(公告)日：2023-08-17

申请号：US18304691

申请日：2023-04-21

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yu HUANG ,  Weiwei ZHANG

IPC分类号： G01R31/3183 ,  G01R31/3177 ,  H03K19/21 ,  H03K19/173 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/318335 ,  G01R31/3177 ,  G01R31/31713 ,  G01R31/318536 ,  H03K19/21 ,  H03K19/1733 ,  G01R31/2834

摘要： This application provides decompression circuits. An example decompression circuit includes a plurality of sub-circuits. The sub-circuit includes a plurality of cellular automaton (CA) circuits and a phase shifter. Each of the plurality of CA circuits includes a first XOR circuit and a register. The first XOR circuit includes a first input end, a second input end, and an output end. A data input end of the register is coupled to the output end of the first XOR circuit. A data output end of the register is coupled to the first input end of the first XOR circuit and an input end of the phase shifter. The data output end of the register is further coupled to the second input end of the first XOR circuit in a different CA circuit. The phase shifter is configured to output a test signal.

公开(公告)号：US11705905B1

公开(公告)日：2023-07-18

申请号：US17550908

申请日：2021-12-14

申请人： Kepler Computing Inc.

发明人： Amrita Mathuriya ,  Rafael Rios ,  Ikenna Odinaka ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC分类号： H03K19/173 ,  H03K19/20 ,  H10B53/20

CPC分类号： H03K19/1733 ,  H03K19/20 ,  H10B53/20

摘要： An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

公开(公告)号：US20180330767A1

公开(公告)日：2018-11-15

申请号：US15595171

申请日：2017-05-15

申请人： Micron Technology, Inc.

发明人： Perry V. Lea ,  Troy A. Manning

IPC分类号： G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G06F12/02 ,  G06F3/06

CPC分类号： G11C7/1006 ,  G06F3/0683 ,  G06F12/02 ,  G06F12/0238 ,  G06F13/124 ,  G06F2003/0692 ,  H03K19/1733

摘要： The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US09997214B1

公开(公告)日：2018-06-12

申请号：US15637711

申请日：2017-06-29

申请人： Cadence Design Systems, Inc.

发明人： Vinod Kumar ,  Tara Vishin

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C14/00 ,  G11C5/14 ,  G11C11/40 ,  H03K19/173 ,  H03K19/00 ,  H03K19/0185

CPC分类号： G11C7/1057 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1069 ,  G11C11/40 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4096 ,  G11C14/0009 ,  G11C2207/105 ,  H03K19/00 ,  H03K19/0005 ,  H03K19/0185 ,  H03K19/018521 ,  H03K19/173 ,  H03K19/1733

摘要： Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.

公开(公告)号：US20180159538A1

公开(公告)日：2018-06-07

申请号：US15607588

申请日：2017-05-29

申请人： STMicroelectronics S.r.l.

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo

IPC分类号： H03K19/21

CPC分类号： H03K19/21 ,  G08C2201/91 ,  H03K19/1733 ,  H03K19/1737 ,  H03K2217/94021 ,  H04L61/2038 ,  H04L61/6072

摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

公开(公告)号：US20180159537A1

公开(公告)日：2018-06-07

申请号：US15877224

申请日：2018-01-22

申请人： CALLAHAN CELLULAR L.L.C.

发明人： Raminda Udaya Madurawe

IPC分类号： H03K19/173 ,  H03K19/177 ,  H01L23/525 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118 ,  H01L27/12 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108

CPC分类号： H03K19/1735 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/11803 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2924/0002 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/1776 ,  H01L2924/00

摘要： A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

公开(公告)号：US20180091155A1

公开(公告)日：2018-03-29

申请号：US15701478

申请日：2017-09-12

申请人： Infineon Technologies AG

发明人： Thomas KUENEMUND

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K19/17708 ,  H03K19/00315 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/1733 ,  H03K19/17768 ,  H03K19/20

摘要： According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ⋀ b ) ⋁ ( p 1 ⋀ a ) ⋁ ( p 2 ⋀ b ) ) _ ⋀ ( p 3 ⋁ b ⋁ a ) ) ⋁ ( a ⋀ b ⋀ p 4 ) _ .

公开(公告)号：US09692421B2

公开(公告)日：2017-06-27

申请号：US13667292

申请日：2012-11-02

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Kiyoshi Kato ,  Jun Koyama

IPC分类号： H01L25/00 ,  H03K19/00 ,  H03K19/173 ,  G11C14/00 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H03K3/356 ,  G11C16/02 ,  H01L27/1156

CPC分类号： H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

摘要： A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.