公开(公告)号：US20060091551A1

公开(公告)日：2006-05-04

申请号：US10977596

申请日：2004-10-29

Applicant: Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

Inventor： Chun-Chieh Lin ,  Shih-Wei Chou ,  Minghsing Tsai

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76816 ,  C25D3/58 ,  C25D5/022 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877

Abstract: A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract translation: 一种形成具有改善的体积特性的铜填充半导体特征的方法，包括提供具有包括用于形成半导体特征的开口的工艺表面的半导体工艺晶片; 在所述开口上沉积至少一种含金属掺杂剂层以形成与随后沉积的铜层的热扩散关系; 沉积所述铜层以基本上填充所述开口; 以及对所述半导体工艺晶片进行热处理足以使所述金属掺杂剂的至少一部分分布在包含所述铜层晶界的一部分的所述铜层的周边的至少一部分的时间段内收集。

公开(公告)号：US20060081952A1

公开(公告)日：2006-04-20

申请号：US11163118

申请日：2005-10-05

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L43/00

CPC classification number: H01L27/228 ,  H01L43/08

Abstract: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

Abstract translation: 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

公开(公告)号：US20050252443A1

公开(公告)日：2005-11-17

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20050170594A1

公开(公告)日：2005-08-04

申请号：US11093847

申请日：2005-03-30

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，该区域和漏极区域包括具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

公开(公告)号：US06921913B2

公开(公告)日：2005-07-26

申请号：US10379033

申请日：2003-03-04

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

公开(公告)号：US06875655B2

公开(公告)日：2005-04-05

申请号：US10802564

申请日：2004-03-17

Applicant: Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

Inventor： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

IPC: H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Abstract translation: 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

公开(公告)号：US20050045949A1

公开(公告)日：2005-03-03

申请号：US10650445

申请日：2003-08-28

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract translation: 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

公开(公告)号：US06816748B1

公开(公告)日：2004-11-09

申请号：US09686895

申请日：2000-10-12

Applicant: Ting Kuo Chen ,  Wen Chin Kuo ,  Yong Sen Liao ,  Chun Chieh Lin

Inventor： Ting Kuo Chen ,  Wen Chin Kuo ,  Yong Sen Liao ,  Chun Chieh Lin

IPC: G06F1900

CPC classification number: B24B37/0053 ,  B24B37/04 ,  B24B49/00 ,  H01L21/67253 ,  H01L21/67288

Abstract: The present invention proposes a smart automatic recording system and method for monitoring wafer fragmentation, which system comprises a plurality of photographing devices, a multiple-image transmitter, a multiple-image receiver, and a PC. The photographing devices are used to monitor the circumstances when wafers are polished. The photographed images are then transferred to the multiple-image receiver by the multiple-image transmitter. After the multiple-image receiver receives the image signals, it merges the images captured at the same time into the same image frame. Next, the multiple-image receiver transfers the image signal to the input terminal of an image-capturing card in the PC. The PC also receives the wafer-entry and wafer-exit signals and the signal of wafer fragmentation transferred from the port of the polishing apparatus. The present invention can be exploited to facilitate judgement, diagnosis, genuine factor verification, or engineering improvement and management for associated technicians.

公开(公告)号：US06656844B1

公开(公告)日：2003-12-02

申请号：US09981437

申请日：2001-10-18

Applicant: Chun-Chieh Lin ,  Wong-Cheng Shih

Inventor： Chun-Chieh Lin ,  Wong-Cheng Shih

IPC: H01L21301

CPC classification number: H01L21/32136 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

Abstract: A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.

Abstract translation: 已经开发了形成具有增加的表面积的DRAM电容器结构的方法。 该方法具有位于由单个多晶硅存储节点结构组成的阵列上方的多晶硅顶板结构。 每个多晶硅存储节点结构包括高垂直特征，并且通过从存储节点结构的第一组表面去除对接的绝缘体层来获得额外的表面积。 绝缘体层保持对接到第二组存储节点结构表面，以防止后续处理序列期间存储节点结构的高垂直特征的崩溃。