公开(公告)号：US20110014770A1

公开(公告)日：2011-01-20

申请号：US12591722

申请日：2009-11-30

Applicant: Ki-yeon Park ,  Cha-young Yoo ,  Jong-cheol Lee ,  Jun-noh Lee

Inventor： Ki-yeon Park ,  Cha-young Yoo ,  Jong-cheol Lee ,  Jun-noh Lee

IPC: H01G9/00 ,  H01L21/469

CPC classification number: H01G4/33 ,  C23C16/45531 ,  C23C16/45542 ,  C23C16/45553 ,  H01G4/085 ,  H01G4/1209 ,  H01L21/02159 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31641

Abstract: A method of forming a dielectric thin film of a semiconductor device, the method including supplying a first nuclear atom precursor source and a second nuclear atom precursor source having different thermal decomposition temperatures to a substrate and forming a chemical adsorption layer including first nuclear atoms and second nuclear atoms on the substrate. A reactant including oxygen atoms may be supplied to the substrate on which the chemical adsorption layer is formed. An atomic layer including an oxide of the first nuclear atoms and the second nuclear atoms may be formed on the chemical adsorption layer.

Abstract translation: 一种形成半导体器件的电介质薄膜的方法，该方法包括向基片提供具有不同热分解温度的第一核原子前体源和第二核原子前体源，并形成包括第一核原子和第二核原子的化学吸附层 核原子在基底上。 可以将包含氧原子的反应物供给到其上形成有化学吸附层的基板。 可以在化学吸附层上形成包含第一核原子和第二核原子的氧化物的原子层。

公开(公告)号：US07759718B2

公开(公告)日：2010-07-20

申请号：US11865869

申请日：2007-10-02

Applicant: Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Im ,  Jae-hyun Yeo ,  Hoon-sang Choi ,  Eun-ae Chung

Inventor： Sang-yeol Kang ,  Jong-cheol Lee ,  Ki-vin Im ,  Jae-hyun Yeo ,  Hoon-sang Choi ,  Eun-ae Chung

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/31641 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L28/40

Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.

Abstract translation: 公开了一种在适用于半导体器件的电容器中形成电介质层的方法。 该方法包括形成第一ZrO 2层，在第一ZrO 2层上使用等离子体处理形成界面层，以及在界面层上形成第二ZrO 2层。

公开(公告)号：US20090309187A1

公开(公告)日：2009-12-17

申请号：US12544500

申请日：2009-08-20

Applicant: Jae-hyoung Choi ,  Cha-young Yoo ,  Jong-cheol Lee ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Hoon-sang Choi ,  Se-hoon Oh ,  Se-hwi Cho

Inventor： Jae-hyoung Choi ,  Cha-young Yoo ,  Jong-cheol Lee ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Hoon-sang Choi ,  Se-hoon Oh ,  Se-hwi Cho

IPC: H01L29/92 ,  H01G4/06

CPC classification number: H01L28/40 ,  H01L27/10852 ,  H01L28/91

Abstract: Provided is a semiconductor device including a multi-layer dielectric structure and a method of fabricating the semiconductor device. According to one example embodiment, the semiconductor device includes a capacitor comprising: first and second electrodes facing each other; at least one first dielectric layer that is disposed between the first and second electrodes, the at least one first dielectric layer comprising a first high-k dielectric layer doped with silicon; and at least one second dielectric layer that is disposed between the at least one first dielectric layer and any of the first and second electrodes, the at least one second dielectric layer having a higher crystallization temperature than that of the first dielectric layer.

Abstract translation: 提供了包括多层电介质结构的半导体器件和制造该半导体器件的方法。 根据一个示例性实施例，半导体器件包括电容器，包括：彼此面对的第一和第二电极; 设置在所述第一和第二电极之间的至少一个第一介电层，所述至少一个第一介电层包括掺杂有硅的第一高k电介质层; 以及设置在所述至少一个第一介电层和所述第一和第二电极中的任一个之间的至少一个第二电介质层，所述至少一个第二电介质层具有比所述第一介电层的结晶温度更高的结晶温度。

公开(公告)号：US07616512B2

公开(公告)日：2009-11-10

申请号：US12347233

申请日：2008-12-31

Applicant: Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC: G11C7/00

CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

公开(公告)号：US20090154265A1

公开(公告)日：2009-06-18

申请号：US12347239

申请日：2008-12-31

Applicant: Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

Inventor： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

IPC: G11C11/416 ,  G11C8/00

CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

Abstract translation: 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

公开(公告)号：US20090147500A1

公开(公告)日：2009-06-11

申请号：US12173176

申请日：2008-07-15

Applicant: Jun Seok AN ,  Jong Cheol Lee ,  Dae Hyoun Byoun ,  Tae Jun You

Inventor： Jun Seok AN ,  Jong Cheol Lee ,  Dae Hyoun Byoun ,  Tae Jun You

IPC: G02F1/13357 ,  F21V7/00 ,  F21S4/00

CPC classification number: G02F1/133605 ,  G02F1/133604 ,  G02F1/133608

Abstract: A backlight assembly, in which several parts are unified so as to reduce a number of parts used and simplify an assembly process includes lamps emitting light, first lamp sockets, each of which includes a first connection member coupled with one end of each of the lamps so as to be electrically connected to the end of each of the lamps, and a reflection plate to reflect the light emitted from the lamps, and including socket fixing units formed integrally therewith to respectively fix the first lamp sockets. Each of the socket fixing units includes a socket fixing groove formed on a bottom plane of the reflection plate.

Abstract translation: 一种背光组件，其中多个部件是统一的，以便减少使用的部件数量并简化组装过程，包括发射光的灯，第一灯插座，每个灯插座包括与每个灯的一端连接的第一连接部件 以电连接到每个灯的端部，以及反射板，用于反射从灯发射的光，并且包括与其一体形成的插座固定单元，以分别固定第一灯插座。 每个插座固定单元包括形成在反射板的底平面上的插座固定槽。

公开(公告)号：US07482677B2

公开(公告)日：2009-01-27

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L21/4763

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。

公开(公告)号：US20080121184A1

公开(公告)日：2008-05-29

申请号：US11781334

申请日：2007-07-23

Applicant: Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

Inventor： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

IPC: B08B5/00 ,  C23C16/00

CPC classification number: C23C16/45525 ,  C23C16/4401 ,  C23C16/45544

Abstract: Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.

Abstract translation: 提供了一种在电介质层沉积工艺期间清洁原子层沉积设备的蒸发器的原位方法，以防止蒸发器和原子层沉积设备中的喷嘴堵塞。 在电介质层沉积过程中，重复以下步骤：将用于电介质层沉积的第一源气体供应到原子层沉积设备的腔室中; 净化第一源气; 将第二源气体供应到原子层沉积设备的腔室中; 吹扫第二源气体时，在供给用于电介质层沉积的第一源气体并再次供应第一源气体之前执行清洗蒸发器的原位方法。

公开(公告)号：US20080087930A1

公开(公告)日：2008-04-17

申请号：US11733943

申请日：2007-04-11

Applicant: Jong-Cheol Lee ,  Ki-Vin Im ,  Hoon-Sang Choi ,  Eun-Ae Chung ,  Sang-Yeol Kang

Inventor： Jong-Cheol Lee ,  Ki-Vin Im ,  Hoon-Sang Choi ,  Eun-Ae Chung ,  Sang-Yeol Kang

IPC: H01L27/108 ,  H01G4/008 ,  H01L21/20

CPC classification number: H01L28/60 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01L27/10852

Abstract: A capacitor includes a first electrode having a conductive pattern and an anti-oxidation pattern contacting the conductive pattern and a second electrode overlapping the first electrode. The capacitor further includes a capacitor dielectric layer disposed between the first and second electrodes, and having a blanket dielectric layer and a partial dielectric layer. The blanket dielectric layer is disposed between the first and second electrodes, and the partial dielectric layer is disposed between the blanket dielectric layer and the anti-oxidation pattern.

Abstract translation: 电容器包括具有导电图案的第一电极和与导电图案接触的抗氧化图案和与第一电极重叠的第二电极。 电容器还包括设置在第一和第二电极之间的电容器介质层，并且具有覆盖介电层和部分电介质层。 覆盖介电层设置在第一和第二电极之间，并且部分电介质层设置在覆盖电介质层和抗氧化图案之间。

公开(公告)号：US20080023746A1

公开(公告)日：2008-01-31

申请号：US11881562

申请日：2007-07-27

Applicant: Hoon-Sang Choi ,  Jong-Cheol Lee ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Sang-Yeol Kang

Inventor： Hoon-Sang Choi ,  Jong-Cheol Lee ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Sang-Yeol Kang

IPC: H01L29/92 ,  H01L21/31

CPC classification number: H01L21/02194 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/91

Abstract: A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfxZr1-xO; 0

Abstract translation: 形成半导体器件的方法包括将半导体衬底装载到反应室中，并将含有铪和锆的金属有机前体提供到反应室中以形成铪锆氧化物（Hf x Zr z 1-x O; 0