公开(公告)号：US20190363053A1

公开(公告)日：2019-11-28

申请号：US15985838

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Minghao Tang ,  Rui Chen ,  Dongyue Yang ,  Haiting Wang ,  Erik Geiss ,  Scott Beasor

IPC: H01L23/544

Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.

公开(公告)号：US20190333993A1

公开(公告)日：2019-10-31

申请号：US15961912

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Ruilong Xie ,  Hui Zang ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  C30B25/04 ,  C30B29/40

Abstract: Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.

公开(公告)号：US20190259668A1

公开(公告)日：2019-08-22

申请号：US15899986

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Haiting Wang ,  Shimpei Yamaguchi ,  Junsic Hong ,  Yong Mo Yang ,  Scott Beasor

IPC: H01L21/8234 ,  H01L27/088

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

公开(公告)号：US10373875B1

公开(公告)日：2019-08-06

申请号：US15928783

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/311 ,  H01L21/762

Abstract: Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10361289B1

公开(公告)日：2019-07-23

申请号：US15933032

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Shahab Siddiqui ,  Haiting Wang ,  Ting-Hsiang Hung ,  Yiheng Xu ,  Beth Baumert ,  Jinping Liu ,  Scott Beasor ,  Yue Zhong ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/78

Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

公开(公告)号：US20190221661A1

公开(公告)日：2019-07-18

申请号：US15869541

申请日：2018-01-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Zhao ,  Ming Hao Tang ,  Haiting Wang ,  Rui Chen ,  Yuping Ren ,  Hui Zang ,  Scott H. Beasor ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/265 ,  H01L27/11 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/423

Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

公开(公告)号：US20190214308A1

公开(公告)日：2019-07-11

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US20190131177A1

公开(公告)日：2019-05-02

申请号：US15794600

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco ,  Wei Zhao ,  Haiting Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L27/088

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.

公开(公告)号：US20180366461A1

公开(公告)日：2018-12-20

申请号：US15627835

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Haiting Wang ,  Daniel Jaeger

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L28/20 ,  H01L28/24 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.