公开(公告)号：US06472754B2

公开(公告)日：2002-10-29

申请号：US09822489

申请日：2001-04-02

申请人： Takashi Nakajima ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara ,  Kentaro Yamada ,  Masayuki Suzuki

发明人： Takashi Nakajima ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shinji Nishihara ,  Masashi Sahara ,  Kentaro Yamada ,  Masayuki Suzuki

IPC分类号： H01L2348

CPC分类号： H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： The object of the invention is to provide such a highly reliable semiconductor device as no defect such as the breakage of a tungsten conductor occurs. This object is achieved by the following means, i.e., a molybdenum film, a tungsten film and another molybdenum film are deposited in this order on an interlayer dielectric film formed on a silicon substrate.

摘要翻译： 本发明的目的是提供这样一种高度可靠的半导体器件，不会出现诸如钨导体断裂的缺陷。 该目的通过以下方式实现，即，将钼膜，钨膜和另一种钼膜依次沉积在形成在硅衬底上的层间电介质膜上。

公开(公告)号：US08859344B2

公开(公告)日：2014-10-14

申请号：US13314154

申请日：2011-12-07

申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L21/82 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US20120077325A1

公开(公告)日：2012-03-29

申请号：US13314154

申请日：2011-12-07

申请人： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L21/20

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

公开(公告)号：US07965022B2

公开(公告)日：2011-06-21

申请号：US12582723

申请日：2009-10-21

申请人： Tomio Iwasaki

发明人： Tomio Iwasaki

IPC分类号： H01L41/047 ,  H01L41/083

CPC分类号： H01L41/083 ,  H01L41/0471 ,  H01L41/0472 ,  H01L41/1871

摘要： A piezoelectric element that is high in piezoelectric performance and large in displacement and is reliable is provided. The piezoelectric element includes a piezoelectric material containing BaTi2O5 as the principal constituent material and an inner electrode that applies voltage to the piezoelectric material. In this piezoelectric element, an electrode material (a mixture of Ru and RuO2) excellent in lattice matching with the piezoelectric material BaTi2O5 is used as the principal constituent material of the inner electrode.

摘要翻译： 提供压电性能高，位移大且可靠的压电元件。 压电元件包括​​含有BaTi2O5作为主要构成材料的压电材料和向压电材料施加电压的内部电极。 在该压电元件中，使用与压电体BaTi2O5的晶格匹配优异的电极材料（Ru和RuO2的混合物）作为内部电极的主要构成材料。

公开(公告)号：US07777343B2

公开(公告)日：2010-08-17

申请号：US11449814

申请日：2006-06-09

申请人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

发明人： Junji Noguchi ,  Takayuki Oshima ,  Noriko Miura ,  Kensuke Ishikawa ,  Tomio Iwasaki ,  Kiyomi Katsuyama ,  Tatsuyuki Saito ,  Tsuyoshi Tamaru ,  Hizuru Yamaguchi

IPC分类号： H01L23/52

CPC分类号： H01L21/76811 ,  H01L21/314 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76822 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

摘要翻译： 提高了布线的可靠性，其中包括以铜为主要成分的主导电膜。 在包括用作下层布线的布线的上表面的绝缘膜上形成由铜阻隔性优异的碳氮化硅膜形成的绝缘膜; 在绝缘膜上形成由与低介电常数材料膜具有优异粘合性的碳化硅膜形成的绝缘膜; 在绝缘膜上形成由作为层间绝缘膜的低介电常数材料形成的绝缘膜; 然后形成作为上层布线的布线。

公开(公告)号：US20100193957A1

公开(公告)日：2010-08-05

申请号：US12759335

申请日：2010-04-13

申请人： Tomio Iwasaki ,  Hideo Miura

发明人： Tomio Iwasaki ,  Hideo Miura

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {l ap−anl/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lbp−bn l/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp) }

摘要翻译： 提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触 与导体膜。 在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差， ，构成具有相邻膜的最小自由能的平面的矩形单位电池，即{l ap-anl / ap}×100 = A（％）和矩形单元电池的长边，bp之间的差异， 构成具有相邻膜的最小自由能的构成平面的矩形单元电池的导体膜和长边bn的最小自由能的平面{lbp-bn l / bp}×100 = B（％ ）满足{A + B×（ap / bp）} <13的不等式。 在此，导体膜的扩散被延迟。

公开(公告)号：US07674668B2

公开(公告)日：2010-03-09

申请号：US12005444

申请日：2007-12-26

申请人： Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

发明人： Norio Ishitsuka ,  Nobuyoshi Hattori ,  Tomio Iwasaki

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： After a gate electrode is formed on a main surface of a semiconductor substrate, low concentration layers are formed on the main surface of the semiconductor substrate by implanting impurities therein, with using the gate electrode as a mask. Thereafter, first sidewalls and second sidewalls are formed on the both side surfaces of the gate electrode. Subsequently, nitrogen or the like is ion-implanted into the semiconductor substrate, with using the first sidewalls, the second sidewalls and the gate electrode as a mask, thereby forming a crystallization-control region (CCR) on the main surface of the semiconductor substrate. Then, after the second sidewalls are removed, high concentration layers for a source and a drain are formed on the main surface of the semiconductor substrate.

摘要翻译： 在半导体衬底的主表面上形成栅电极之后，通过使用栅电极作为掩模，在半导体衬底的主表面上注入杂质，形成低浓度层。 此后，在栅电极的两个侧表面上形成第一侧壁和第二侧壁。 随后，使用第一侧壁，第二侧壁和栅电极作为掩模，将氮等离子注入到半导体衬底中，从而在半导体衬底的主表面上形成结晶化控制区域（CCR） 。 然后，在去除第二侧壁之后，在半导体衬底的主表面上形成用于源极和漏极的高浓度层。

公开(公告)号：US20100044672A1

公开(公告)日：2010-02-25

申请号：US12613235

申请日：2009-11-05

申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

公开(公告)号：US20090174061A1

公开(公告)日：2009-07-09

申请号：US12401491

申请日：2009-03-10

申请人： Yasuhiro NAKA ,  Tomio Iwasaki ,  Hidekazu Okuda ,  Yuji Fujii

发明人： Yasuhiro NAKA ,  Tomio Iwasaki ,  Hidekazu Okuda ,  Yuji Fujii

IPC分类号： H01L23/48 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.

摘要翻译： 为了防止在制造过程中由于热负荷等而在半导体器件的焊料接合焊盘中的膜剥离，由此导致剥离，可以采用衬垫结构，其中Cr膜具有良好的粘合性 在形成于硅或氧化硅膜上的Ti膜或Ti化合物膜之间插入Ti膜或Ti化合物膜和Ni膜（或Cu膜），Ni膜（或Cu膜）为 连接到焊料。 此外，为了防止在Ti膜或Ti化合物膜与氧化硅膜之间的界面处的剥离，Cr膜形成在比Ti膜或Ti化合物膜更大的面积上。

公开(公告)号：US07534507B2

公开(公告)日：2009-05-19

申请号：US11243012

申请日：2005-10-03

申请人： Reiko Arai ,  Yoshiyuki Hirayama ,  Yuzuru Hosoe ,  Tomio Iwasaki ,  Yoko Ogawa ,  Ikuko Takekuma

发明人： Reiko Arai ,  Yoshiyuki Hirayama ,  Yuzuru Hosoe ,  Tomio Iwasaki ,  Yoko Ogawa ,  Ikuko Takekuma

IPC分类号： G11B5/66

CPC分类号： G11B5/732 ,  G11B5/656 ,  G11B5/851

摘要： Embodiments of the invention are directed to a medium which provides high media S/N and good corrosion resistance. According to one embodiment, in a perpendicular magnetic recording medium at least comprising a soft-magnetic underlayer, a seed layer, an intermediate layer, a magnetic recording layer and an overcoat layer which are stacked over a substrate in order, the magnetic recording layer has a granular structure which includes many columnar grains of CoCrPt alloy and a grain boundary layer containing an oxide, the seed layer is made of TaNi alloy or TaTi alloy and the intermediate layer is made of Ru or Ru alloy which contains 80 at. % Ru or more.

摘要翻译： 本发明的实施方案涉及提供高介质S / N和良好耐腐蚀性的介质。 根据一个实施例，在依次层叠在基板上的至少包括软磁性底层，种子层，中间层，磁记录层和覆盖层的垂直磁记录介质中，磁记录层具有 包括许多CoCrPt合金的柱状晶粒和含有氧化物的晶界层的粒状结构，种子层由TaNi合金或TaTi合金制成，中间层由含有80at的Ru或Ru合金制成。 ％Ru或更多。