公开(公告)号：US10522510B2

公开(公告)日：2019-12-31

申请号：US15575323

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Jacob M. Jensen ,  Patrick Morrow ,  Paul B. Fischer

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L23/00 ,  H01L21/683

Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.

公开(公告)号：US10236282B2

公开(公告)日：2019-03-19

申请号：US15026268

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Rajashree Baskaran ,  Paul B. Fischer

IPC: H01L27/02 ,  H01L21/8258 ,  H01L21/683 ,  H01L23/528 ,  H01L29/16 ,  H01L29/20 ,  H01L27/085

Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

公开(公告)号：US20190057950A1

公开(公告)日：2019-02-21

申请号：US16077568

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Patrick Morrow ,  Paul B. Fischer ,  Kimin Jun

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/60 ,  H01L25/065

Abstract: An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.

公开(公告)号：US10043797B2

公开(公告)日：2018-08-07

申请号：US15124808

申请日：2014-06-23

Applicant: INTEL CORPORATION

Inventor： Kimin Jun ,  Patrick Morrow

IPC: H01L29/00 ,  H01L27/088 ,  H01L29/775 ,  H01L27/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11273 ,  H01L28/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7926

Abstract: Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing. Processing can be performed in multiple iterations, for example, to provide multi-level/stacked vertical transistor circuit architectures of any standard and/or custom configuration.

公开(公告)号：US09935191B2

公开(公告)日：2018-04-03

申请号：US15122627

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Sansaptak Dasgupta ,  Alejandro X. Levander ,  Patrick Morrow

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/78 ,  H01L29/04 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

公开(公告)号：US20250112196A1

公开(公告)日：2025-04-03

申请号：US18478843

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Johanna Swan ,  Adel Elsherbini ,  Thomas L. Sounart ,  Tushar Kanti Talukdar ,  Brandon M. Rawlings ,  Kimin Jun ,  Andrey Vyatskikh ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/373 ,  H01L23/38 ,  H01L23/433 ,  H01L23/538 ,  H10N19/00

Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.

公开(公告)号：US20250112177A1

公开(公告)日：2025-04-03

申请号：US18374516

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Thomas Sounart ,  Yi Shi ,  Michael Baker ,  Adel Elsherbini ,  Kimin Jun ,  Xavier Brun ,  Wenhao Li

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/786

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.

公开(公告)号：US20250108459A1

公开(公告)日：2025-04-03

申请号：US18478770

申请日：2023-09-29

Applicant: INTEL CORPORATION

Inventor： Andrey Vyatskikh ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Thomas L. Sounart ,  Jeffery D. Bielefeld ,  Grant M. Kloster ,  Carlos Bedoya Arroyave ,  Golsa Naderi ,  Adel Elsherbini

IPC: B23K26/40 ,  B23K26/53 ,  B23K101/40 ,  B23K103/00

Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.

公开(公告)号：US20250105136A1

公开(公告)日：2025-03-27

申请号：US18473887

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Thomas Lee Sounart ,  Tushar Kanti Talukdar ,  Johanna Marie Swan ,  Uygar Avci

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: Capacitors for use with integrated circuit packages are disclosed. An example apparatus includes a semiconductor substrate, a metal layer coupled to the semiconductor substrate, a dielectric layer coupled to the metal layer, the dielectric layer including a capacitor disposed therein, and an interface layer positioned between the metal layer and the dielectric layer, the interface layer in contact with the dielectric layer and in contact with the metal layer.

公开(公告)号：US12176323B2

公开(公告)日：2024-12-24

申请号：US17728813

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Johanna M. Swan ,  Patrick Morrow ,  Kimin Jun ,  Brennen Mueller ,  Paul B. Fischer

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.