公开(公告)号：US20150115459A1

公开(公告)日：2015-04-30

申请号：US14065451

申请日：2013-10-29

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Andrew T. Kim ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76849 ,  H01L21/76898 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Abstract translation: 本公开通常提供具有TSV的集成电路（IC）结构以及制造IC结构和TSV的方法。 根据本发明的实施例的IC结构可以包括嵌入在基板内的贯穿半导体通孔（TSV），TSV具有轴向端; 以及与TSV的轴向端接触的金属盖，其中金属帽具有比TSV更大的电阻率。

公开(公告)号：US08906799B1

公开(公告)日：2014-12-09

申请号：US13953058

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.

Abstract translation: 公开了一种用于防止由于电迁移和时间依赖介电击穿而导致的集成电路故障的方法和结构。 在金属互连线（通常为铜（Cu））上选择性地形成随机图案化的金属覆盖层，金属帽段之间的间隙距离小于临界长度（对于短长度效应）。 由于Cu /金属帽接口的扩散率比对于Cu /电介质盖接口的扩散率低，所以具有金属帽的区域用作扩散阻挡层。

公开(公告)号：US20140332923A1

公开(公告)日：2014-11-13

申请号：US14024694

申请日：2013-09-12

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.

Abstract translation: 一种电熔丝结构，包括具有由第一导体制成的第一区域和由第二导体制成的第二区域的熔丝连接。 第一导体和第二导体处于相同的布线层。 第一导体具有比第二导体更高的电阻。 第一导体比第二导体具有更高的电迁移阻力。 第一区域和第二区域具有共同的宽度。 第一区域的长度比第二区域的长度长。

公开(公告)号：US20140306322A1

公开(公告)日：2014-10-16

申请号：US13860753

申请日：2013-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert D. Edwards ,  Jeffrey P. Gambino ,  Charles F. Musante ,  Ping-Chuan Wang

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/27 ,  H01L2224/0345 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface.

Abstract translation: 提供了一种半导体结构及其制造方法及其结构。 该半导体结构包括包括半导体层和嵌入其中的多个TSV的衬底。 至少一个TSV具有从衬底的背面延伸的TSV尖端。 半导体结构还包括位于基板的背面上的多层金属接触结构。 多层金属接触结构至少包括覆盖基板的背面的导电层，并且覆盖TSV尖端的突出表面。 导电层具有非平面的第一表面和与第一表面相对的基本平坦的第二表面。

公开(公告)号：US20140234990A1

公开(公告)日：2014-08-21

申请号：US14263067

申请日：2014-04-28

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  J. Edwin Hostetter, JR. ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  G01R31/275 ,  H01L21/326 ,  H01L29/7833

Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.

Abstract translation: 用于修复晶体管的方法和装置可以包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极预定时间。 以这种方式，晶体管结构可以被修复或返回以在原始操作特性或附近操作。

公开(公告)号：US20140217612A1

公开(公告)日：2014-08-07

申请号：US13760488

申请日：2013-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Wai-Kin Li ,  Erdem Kaltalioglu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.

Abstract translation: 一种电子熔丝结构，包括包含Mx金属的Mx电平和Mx电平以上的Mx + 1电平，Mx + 1电平包括Mx + 1金属和将Mx金属电连接到Mx + 1金属的通孔 垂直取向，其中Mx + 1金属包括厚部分和薄部分，并且其中Mx金属，Mx + 1金属和通孔基本上填充有导电材料。

公开(公告)号：US20140197865A1

公开(公告)日：2014-07-17

申请号：US13739151

申请日：2013-01-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang ,  Emmanuel Yashchin

IPC: H03K3/313

CPC classification number: H03K3/84 ,  H03K3/012 ,  H03K3/313 ,  H03K5/01

Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

Abstract translation: 片上真实噪声发生器，包括具有低电压，高噪声齐纳二极管的嵌入式噪声源和原位闭环齐纳二极管功率控制电路。 本发明提出使用重掺杂多晶硅和硅p-n二极管结构来最小化击穿电压，增加噪声水平和提高可靠性。 本发明还提出了一种原位闭环齐纳二极管控制电路，以保护齐纳二极管免受灾难性烧坏。

公开(公告)号：US08765568B2

公开(公告)日：2014-07-01

申请号：US14048629

申请日：2013-10-08

Applicant: International Business Machines Corporation

Inventor： Joseph M. Lukaitis ,  Deborah M. Massey ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC: H01L23/36

CPC classification number: H01L28/20 ,  H01L23/3677 ,  H01L23/5228 ,  H01L27/0211 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract translation: 制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。 每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。 最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。 一个电阻器被包含在最上层的上方的层中。 垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

公开(公告)号：US20140167772A1

公开(公告)日：2014-06-19

申请号：US14188728

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC: G01R31/327

CPC classification number: H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

公开(公告)号：US20140138751A1

公开(公告)日：2014-05-22

申请号：US13775436

申请日：2013-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Cai ,  Chengwen Pei ,  Robert R. Robison ,  Ping-Chuan Wang

IPC: H01L29/78

CPC classification number: H01L29/41 ,  H01L21/28114 ,  H01L21/82385 ,  H01L29/40 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

Abstract translation: 形成场效应晶体管（FET）器件的方法包括在衬底上形成栅极结构，所述栅极结构包括宽的底部和形成在底部的顶部上的窄部; 所述宽底部包括金属材料并且具有基本上对应于晶体管沟道长度的第一宽度，并且所述窄部分还包括具有小于所述第一宽度的第二宽度的金属材料。