公开(公告)号：US09859303B2

公开(公告)日：2018-01-02

申请号：US15274403

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Wai-Kin Li ,  Chieh-Yu Lin ,  Yannick Daurelle

IPC: H01L27/12 ,  H01L29/40 ,  H01L21/441 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/1211 ,  H01L21/441 ,  H01L21/7624 ,  H01L21/76807 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

公开(公告)号：US09391014B2

公开(公告)日：2016-07-12

申请号：US14825303

申请日：2015-08-13

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L23/522 ,  H01L23/528 ,  H04L9/32 ,  H05K1/02

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

Abstract translation: 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。

公开(公告)号：US20160190005A1

公开(公告)日：2016-06-30

申请号：US15060685

申请日：2016-03-04

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L23/5222 ,  H01L21/0274 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H04L9/3278 ,  H04L2209/12 ,  H05K1/0289 ,  Y10T29/49117 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

公开(公告)号：US09093452B2

公开(公告)日：2015-07-28

申请号：US13790399

申请日：2013-03-08

Applicant: International Business Machines Corporation

Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Wai-Kin Li ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768 ,  H01L23/525 ,  H01L23/34 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/345 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a portion of the first Mx+1 dielectric, forming a second Mx+1 dielectric above the first Mx+1 dielectric and above the conductive path, the first and second Mx+1 dielectrics together form an Mx+1 level, forming a first and a second via in the Mx+1 level, the conductive path extending from the first via to the second via and partially encircling the first via, and forming a first and second Mx+1 metal in the Mx+1 level, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.

Abstract translation: 一种形成电子熔丝的方法，包括形成包括第一和第二Mx金属的Mx级，在Mx级上形成第一Mx + 1介质，在第一Mx + 1介质的一部分上形成导电路径，形成 在第一Mx + 1介质上方的第二Mx + 1电介质并且在导电路径之上，第一和第二Mx + 1电介质一起形成Mx + 1电平，在Mx + 1电平中形成第一和第二通孔，导电 所述第一通孔从所述第一通孔延伸到所述第二通孔并且部分地环绕所述第一通孔，以及在所述Mx + 1级中形成第一和第二Mx + 1金属，所述第一通孔垂直延伸并将所述第一Mx金属电连接到所述第一Mx +1金属，并且第二通孔垂直延伸并电连接第二Mx金属与第二Mx + 1金属。

公开(公告)号：US20150207505A1

公开(公告)日：2015-07-23

申请号：US14158917

申请日：2014-01-20

Applicant: International Business Machines Corporation

Inventor： Kai D. Feng ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC: H03K19/003 ,  H01L27/088 ,  H01L23/58 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/31 ,  H01L27/02

CPC classification number: H03K19/00315 ,  H01L21/26513 ,  H01L21/823425 ,  H01L21/823493 ,  H01L23/544 ,  H01L23/57 ,  H01L27/0203 ,  H01L27/088 ,  H01L2223/54413 ,  H01L2223/5444 ,  H01L2924/0002 ,  H04L9/3278 ,  H01L2924/00

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底和在半导体衬底中形成的阱。 阱包括具有第一离子浓度的第一区域和具有小于第一浓度的第二浓度的至少一个第二区域。 在井上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

公开(公告)号：US20150194320A1

公开(公告)日：2015-07-09

申请号：US14149898

申请日：2014-01-08

Applicant: International Business Machines Corporation

Inventor： SCOTT D. ALLEN ,  Kuang-Jung Chen ,  Huihang Dong ,  Wai-Kin Li

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31056 ,  H01L21/02071 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32139 ,  H01L29/517 ,  H01L29/518

Abstract: A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.

Abstract translation: 在基板上形成电介质材料层和金属材料层的叠层。 第一有机平坦化层，非金属硬掩模层和光致抗蚀剂层依次沉积在金属材料层上。 光致抗蚀剂层被光刻图案化，并且光致抗蚀剂层中的图案通过非金属硬掩模层，第一有机平坦化层和金属材料层转移以形成空腔。 第二有机平面化层沉积在空腔内以及光致抗蚀剂层的剩余部分上。 第二有机平坦化层和光致抗蚀剂层凹入，随后去除非金属硬掩模层。 同时去除第一和第二有机平坦化层的剩余部分，以提供图案化金属材料层的物理暴露表面和电介质材料层的顶表面。

公开(公告)号：US20150035154A1

公开(公告)日：2015-02-05

申请号：US14486493

申请日：2014-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shyng-Tsong Chen ,  Samuel S. Choi ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Wai-Kin Li ,  Christopher J. Penny ,  Shom Ponoth ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.

Abstract translation: 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间，每个通孔开口内的轮廓控制衬里的存在防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

公开(公告)号：US08906799B1

公开(公告)日：2014-12-09

申请号：US13953058

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Wai-Kin Li ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L21/4763 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for preventing integrated circuit failure due to electromigration and time dependent dielectric breakdown is disclosed. A randomly patterned metal cap layer is selectively formed on the metal interconnect lines (typically copper (Cu)) with an interspace distance between metal cap segments that is less than the critical length (for short-length effects). Since the diffusivity is lower for the Cu/metal cap interface than for the Cu/dielectric cap interface, the region with a metal cap serves as a diffusion barrier.

Abstract translation: 公开了一种用于防止由于电迁移和时间依赖介电击穿而导致的集成电路故障的方法和结构。 在金属互连线（通常为铜（Cu））上选择性地形成随机图案化的金属覆盖层，金属帽段之间的间隙距离小于临界长度（对于短长度效应）。 由于Cu /金属帽接口的扩散率比对于Cu /电介质盖接口的扩散率低，所以具有金属帽的区域用作扩散阻挡层。

公开(公告)号：US20140217612A1

公开(公告)日：2014-08-07

申请号：US13760488

申请日：2013-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Wai-Kin Li ,  Erdem Kaltalioglu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.

Abstract translation: 一种电子熔丝结构，包括包含Mx金属的Mx电平和Mx电平以上的Mx + 1电平，Mx + 1电平包括Mx + 1金属和将Mx金属电连接到Mx + 1金属的通孔 垂直取向，其中Mx + 1金属包括厚部分和薄部分，并且其中Mx金属，Mx + 1金属和通孔基本上填充有导电材料。

公开(公告)号：US09515148B2

公开(公告)日：2016-12-06

申请号：US14076871

申请日：2013-11-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics

Inventor： Wai-Kin Li ,  Chieh-Yu Lin ,  Yannick Daurelle

IPC: H01L29/40 ,  H01L21/441 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/768

CPC classification number: H01L27/1211 ,  H01L21/441 ,  H01L21/7624 ,  H01L21/76807 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Abstract translation: 半导体器件包括形成在半导体衬底上的多个栅极，该栅极包括多个外部有源区域（例如CMOS / PMOS区域，源极/漏极区域等）和一个或多个内部有源区域。 隔离器形成在与一个或多个内部有源区域相关联的一个或多个内部门上。 接触杆电连接外部有源区域和/或外部门，并形成在隔离器上。 隔离器将接触杆与一个或多个内部有源区域和/或一个或多个内部门隔离。