公开(公告)号：US10510848B2

公开(公告)日：2019-12-17

申请号：US15576150

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Ying Pang ,  Anand S. Murthy ,  Tahir Ghani ,  Karthik Jambunathan

IPC: H01L29/40 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

公开(公告)号：US20190355725A1

公开(公告)日：2019-11-21

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/108 ,  H01L29/22 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US20190326296A1

公开(公告)日：2019-10-24

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US20190305081A1

公开(公告)日：2019-10-03

申请号：US15941557

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Travis W. LaJoie ,  Abhishek A. Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem O. Ogadhoh ,  Allen B. Gardiner ,  Blake C. Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/764 ,  H01L21/02 ,  H01L29/423 ,  H01L27/105

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US10403752B2

公开(公告)日：2019-09-03

申请号：US15525183

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Glenn A. Glass ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

公开(公告)号：US20190221641A1

公开(公告)日：2019-07-18

申请号：US16327034

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Nabil G. Mistkawi ,  Karthik Jambunathan ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.

公开(公告)号：US10340185B2

公开(公告)日：2019-07-02

申请号：US15624036

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/70 ,  H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/02 ,  H01L23/535 ,  H01L29/06 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20190189755A1

公开(公告)日：2019-06-20

申请号：US16327194

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/167 ,  H01L27/088 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/167 ,  B82Y10/00 ,  H01L27/0886 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66356 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistors including source and drain (S/D) regions employing double-charge dopants. As can be understood based on this disclosure, the use of double-charge dopants for group IV semiconductor material (e.g., Si, Ge, SiGe) either alone or in combination with single-charge dopants (e.g., P, As, B) can decrease the energy barrier at the semiconductor/metal interface between the source and drain regions (semiconductor) and their respective contacts (metal), thereby improving (by reducing) contact resistance at the S/D locations. In some cases, the double-charge dopants may be provided in a top or cap S/D portion of a given S/D region, for example, so that the double-charge doped S/D material is located at the interface of that S/D region and the corresponding contact. The double-charge dopants can include sulfur (S), selenium (Se), and/or tellurium (Te). Other suitable group IV material double-charge dopants will be apparent in light of this disclosure.

公开(公告)号：US10319812B2

公开(公告)日：2019-06-11

申请号：US15789315

申请日：2017-10-20

Applicant: Intel Corporation

Inventor： Milton Clair Webb ,  Mark Bohr ,  Tahir Ghani ,  Szuya S. Liao

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/417

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

公开(公告)号：US10229997B2

公开(公告)日：2019-03-12

申请号：US15576381

申请日：2015-06-23

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Willy Rachmady ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew V. Metz ,  Harold W. Kennel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/775 ,  H01L29/12 ,  H01L27/088 ,  H01L29/205 ,  H01L21/02

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.