公开(公告)号：US08766234B1

公开(公告)日：2014-07-01

申请号：US13728860

申请日：2012-12-27

申请人： Intermolecular, Inc.

发明人： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

摘要： Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

摘要翻译： 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件开关期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。

公开(公告)号：US20140175359A1

公开(公告)日：2014-06-26

申请号：US14194082

申请日：2014-02-28

申请人： Intermolecular Inc.

发明人： Yun Wang ,  Imran Hashim

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

摘要： Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

公开(公告)号：US08723156B2

公开(公告)日：2014-05-13

申请号：US13656908

申请日：2012-10-22

申请人： Intermolecular, Inc.

发明人： Ronald J. Kuse ,  Tony P. Chiang ,  Imran Hashim

IPC分类号： H01L45/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1641

摘要： Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

摘要翻译： 描述了具有改进的开关特性的电阻式开关存储元件，包括具有第一电极和第二电极的存储元件，第一电极和第二电极之间的开关层，包括氧化铪并具有第一厚度，以及耦合层， 所述开关层和所述第二电极，所述耦合层包括包含金属钛并且具有小于所述第一厚度的25％的第二厚度的材料。

公开(公告)号：US20140090596A1

公开(公告)日：2014-04-03

申请号：US14096981

申请日：2013-12-04

申请人： Intermolecular, Inc.

发明人： Gaurav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

IPC分类号： G01R31/28

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US20140073107A1

公开(公告)日：2014-03-13

申请号：US13897050

申请日：2013-05-17

申请人： Intermolecular Inc.

发明人： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC分类号： H01L45/00

CPC分类号： H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

摘要翻译： 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US20130071990A1

公开(公告)日：2013-03-21

申请号：US13677126

申请日：2012-11-14

申请人： Intermolecular, Inc.

发明人： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： H01L21/02

CPC分类号： H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

摘要翻译： 本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。 具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。 在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。 如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺作为反应过程的结果来生产氧化物层 反应。

公开(公告)号：US20130069201A1

公开(公告)日：2013-03-21

申请号：US13675971

申请日：2012-11-13

申请人： Intermolecular, Inc.

发明人： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobumichi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC分类号： H01L49/02

CPC分类号： H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

公开(公告)号：US20130044404A1

公开(公告)日：2013-02-21

申请号：US13657782

申请日：2012-10-22

申请人： Intermolecular, Inc.

发明人： Hanhong Chen ,  Nobumichi Fuchigami ,  Imran Hashim ,  Edward L. Haywood ,  Pragati KUMAR ,  Sandra G. Malhotra ,  Monica Sawkar Mathur ,  Prashant B. Phatak ,  Sunil Shanker

IPC分类号： H01G4/30 ,  H01G4/018

CPC分类号： H01G4/1218 ,  C23C16/405 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/3142 ,  H01L28/40

摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on titanium oxide, to suppress the formation of anatase-phase titanium oxide and (b) related devices and structures. A metal-insulator-metal (“MIM”) stack is formed using an ozone pretreatment process of a bottom electrode (or other substrate) followed by an ALD process to form a TiO2 dielectric, rooted in the use of an amide-containing precursor. Following the ALD process, an oxidizing anneal process is applied in a manner is hot enough to heal defects in the TiO2 dielectric and reduce interface states between TiO2 and electrode; the anneal temperature is selected so as to not be so hot as to disrupt BEL surface roughness. Further process variants may include doping the titanium oxide, pedestal heating during the ALD process to 275-300 degrees Celsius, use of platinum or ruthenium for the BEL, and plural reagent pulses of ozone for each ALD process cycle. The process provides high deposition rates, and the resulting MIM structure has substantially no x-ray diffraction peaks associated with anatase-phase titanium oxide.

摘要翻译： 本公开内容提供（a）制造基于氧化钛的氧化物层（例如电介质层）的方法，以抑制锐钛矿相氧化钛的形成和（b）相关的器件和结构。 使用底部电极（或其他基底）的臭氧预处理随后进行ALD工艺形成金属 - 绝缘体 - 金属（MIM）堆叠，以形成使用含酰胺前体的TiO 2电介质。 在ALD工艺之后，氧化退火工艺的应用热度足以愈合TiO2电介质中的缺陷，并降低TiO2和电极之间的界面态; 选择退火温度以使其不那么热，以致破坏BEL表面粗糙度。 进一步的工艺变型可以包括在ALD工艺期间掺杂氧化钛，基座加热至275-300摄氏度，对于BEL使用铂或钌，对于每个ALD工艺循环使用多个试剂脉冲的臭氧。 该方法提供高沉积速率，并且所得MIM结构基本上没有与锐钛矿相氧化钛相关的x射线衍射峰。

公开(公告)号：US09444047B2

公开(公告)日：2016-09-13

申请号：US14806263

申请日：2015-07-22

申请人： Intermolecular Inc.

发明人： Imran Hashim ,  Tony P. Chiang ,  Vidyut Gopal ,  Yun Wang

IPC分类号： H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC分类号： H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

公开(公告)号：US09281357B2

公开(公告)日：2016-03-08

申请号：US14599843

申请日：2015-01-19

申请人： Intermolecular, Inc. ,  Elpida Memory, Inc

发明人： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC分类号： H01L49/02 ,  H01L27/108

CPC分类号： H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

摘要： A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.